Fix initialization of assoc in assoc array (#2914).

Changes

@@ -11,6 +11,10 @@ contributors that suggested a given feature are shown in []. Thanks!
 Verilator 4.203 devel
 ==========================
 
+**Minor:**
+
+* Fix initialization of assoc in assoc array (#2914). [myftptoyman]
+
 
 Verilator 4.202 2021-04-24
 ==========================

src/V3EmitC.cpp

@@ -1778,19 +1778,19 @@ class EmitCImp final : EmitCStmts {
             // Access std::array as C array
             string cvtarray = (adtypep->subDTypep()->isWide() ? ".data()" : "");
             return emitVarResetRecurse(varp, adtypep->subDTypep(), depth + 1,
-                                       ".atDefault()" + cvtarray);
+                                       suffix + ".atDefault()" + cvtarray);
         } else if (VN_IS(dtypep, ClassRefDType)) {
             return "";  // Constructor does it
         } else if (AstDynArrayDType* adtypep = VN_CAST(dtypep, DynArrayDType)) {
             // Access std::array as C array
             string cvtarray = (adtypep->subDTypep()->isWide() ? ".data()" : "");
             return emitVarResetRecurse(varp, adtypep->subDTypep(), depth + 1,
-                                       ".atDefault()" + cvtarray);
+                                       suffix + ".atDefault()" + cvtarray);
         } else if (AstQueueDType* adtypep = VN_CAST(dtypep, QueueDType)) {
             // Access std::array as C array
             string cvtarray = (adtypep->subDTypep()->isWide() ? ".data()" : "");
             return emitVarResetRecurse(varp, adtypep->subDTypep(), depth + 1,
-                                       ".atDefault()" + cvtarray);
+                                       suffix + ".atDefault()" + cvtarray);
         } else if (AstUnpackArrayDType* adtypep = VN_CAST(dtypep, UnpackArrayDType)) {
             UASSERT_OBJ(adtypep->hi() >= adtypep->lo(), varp,
                         "Should have swapped msb & lsb earlier.");

test_regress/t/t_assoc2.pl

@@ -0,0 +1,21 @@
+#!/usr/bin/env perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2019 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+scenarios(simulator => 1);
+
+compile(
+    );
+
+execute(
+    check_finished => 1,
+    );
+
+ok(1);
+1;

test_regress/t/t_assoc2.v

@@ -0,0 +1,36 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2019 by Wilson Snyder.
+// SPDX-License-Identifier: CC0-1.0
+
+`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d:  got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0);
+`define checks(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d:  got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0);
+`define checkg(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d:  got='%g' exp='%g'\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0);
+
+module t (/*AUTOARG*/
+   // Inputs
+   clk
+   );
+   input clk;
+
+   integer cyc=0;
+
+   // associative array of an associative array
+   logic [31:0] a [logic [31:0]][logic [63:0]];
+
+   always @ (posedge clk) begin
+      cyc <= cyc + 1;
+      if (cyc == 1) begin
+         a[5][8] = 8;
+         a[5][9] = 9;
+      end
+      else if (cyc == 2) begin
+         `checkh(a[5][8], 8);
+         `checkh(a[5][9], 9);
+         $write("*-* All Finished *-*\n");
+         $finish;
+      end
+   end
+
+endmodule