Fix missing UNUSED warnings with --coverage (#3736).

Changes

@@ -17,6 +17,7 @@ Verilator 5.003 devel
 * Support named properties (#3667). [Ryszard Rozak, Antmicro Ltd]
 * Internal AST improvements, also affect XML format (#3721). [Geza Lore]
 * Fix return type of $countbits functions to int (#3725). [Ryszard Rozak, Antmicro Ltd]
+* Fix missing UNUSED warnings with --coverage (#3736). [alejandro-castro-ortegon]
 
 
 Verilator 5.002 2022-10-29

src/V3Coverage.cpp

@@ -123,12 +123,13 @@ private:
         m_modp->addStmtsp(declp);
         UINFO(9, "new " << declp << endl);
 
-        AstCoverInc* const incp = new AstCoverInc(fl, declp);
+        AstCoverInc* const incp = new AstCoverInc{fl, declp};
         if (!trace_var_name.empty() && v3Global.opt.traceCoverage()) {
-            AstVar* const varp = new AstVar(incp->fileline(), VVarType::MODULETEMP, trace_var_name,
+            FileLine* const fl_nowarn = new FileLine{incp->fileline()};
-                                            incp->findUInt32DType());
+            fl_nowarn->modifyWarnOff(V3ErrorCode::UNUSEDSIGNAL, true);
+            AstVar* const varp = new AstVar{fl_nowarn, VVarType::MODULETEMP, trace_var_name,
+                                            incp->findUInt32DType()};
             varp->trace(true);
-            varp->fileline()->modifyWarnOff(V3ErrorCode::UNUSEDSIGNAL, true);
             m_modp->addStmtsp(varp);
             UINFO(5, "New coverage trace: " << varp << endl);
             AstAssign* const assp = new AstAssign(
@@ -281,18 +282,18 @@ private:
 
                 // Add signal to hold the old value
                 const string newvarname = std::string{"__Vtogcov__"} + nodep->shortName();
+                FileLine* const fl_nowarn = new FileLine{nodep->fileline()};
+                fl_nowarn->modifyWarnOff(V3ErrorCode::UNUSEDSIGNAL, true);
                 AstVar* const chgVarp
-                    = new AstVar(nodep->fileline(), VVarType::MODULETEMP, newvarname, nodep);
+                    = new AstVar{fl_nowarn, VVarType::MODULETEMP, newvarname, nodep};
-                chgVarp->fileline()->modifyWarnOff(V3ErrorCode::UNUSEDSIGNAL, true);
                 m_modp->addStmtsp(chgVarp);
 
                 // Create bucket for each dimension * bit.
                 // This is necessarily an O(n^2) expansion, which is why
                 // we limit coverage to signals with < 256 bits.
 
-                ToggleEnt newvec{std::string{""},
+                ToggleEnt newvec{std::string{""}, new AstVarRef{fl_nowarn, nodep, VAccess::READ},
-                                 new AstVarRef{nodep->fileline(), nodep, VAccess::READ},
+                                 new AstVarRef{fl_nowarn, chgVarp, VAccess::WRITE}};
-                                 new AstVarRef{nodep->fileline(), chgVarp, VAccess::WRITE}};
                 toggleVarRecurse(nodep->dtypeSkipRefp(), 0, newvec, nodep, chgVarp);
                 newvec.cleanup();
             }

test_regress/t/t_cover_unused_bad.out

@@ -0,0 +1,7 @@
+%Warning-UNUSEDSIGNAL: t/t_cover_unused_bad.v:14:10: Signal is not used: 'unu3'
+                                                   : ... In instance t
+   14 |    logic unu3 = 0;
+      |          ^~~~
+                       ... For warning description see https://verilator.org/warn/UNUSEDSIGNAL?v=latest
+                       ... Use "/* verilator lint_off UNUSEDSIGNAL */" and lint_on around source to disable this message.
+%Error: Exiting due to

test_regress/t/t_cover_unused_bad.pl

@@ -0,0 +1,20 @@
+#!/usr/bin/env perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003-2009 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+scenarios(linter => 1);
+
+lint(
+    verilator_flags2 => ["-Wall -Wno-DECLFILENAME --coverage"],
+    fails => 1,
+    expect_filename => $Self->{golden_filename},
+    );
+
+ok(1);
+1;

test_regress/t/t_cover_unused_bad.v

@@ -0,0 +1,19 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2022 by Wilson Snyder.
+// SPDX-License-Identifier: CC0-1.0
+
+module t (/*AUTOARG*/
+   // Inputs
+   clk
+   );
+
+   input clk;
+
+   logic unu3 = 0;
+
+   logic isusd = 0;
+   cover property (@(posedge clk) isusd == 0);
+
+endmodule