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Add warning on slice selection out of bounds, bug875.

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This commit is contained in:
Wilson Snyder 2015-01-25 16:32:46 -05:00
parent a6743588b6
commit e5af46d3fb
9 changed files with 69 additions and 18 deletions
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2
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@ -9,6 +9,8 @@ indicates the contributor was also the author of the fix; Thanks!
**** Support cast operator with expression size, bug865. [Iztok Jeras]
**** Add warning on slice selection out of bounds, bug875. [Cong Van Nguyen].
**** Fix member select error broke in 3.868, bug867. [Iztok Jeras]
**** Fix $sccanf from string, bug866. [David Pierce]

9
src/V3Width.cpp
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@ -660,6 +660,15 @@ private:
}
}
if (!m_doGenerate) {
// Must check bounds before adding a select that truncates the bound
// Note we've already subtracted off LSB
if (nodep->bitp()->castConst() && (nodep->bitp()->castConst()->toSInt() > (frommsb-fromlsb)
|| nodep->bitp()->castConst()->toSInt() < 0)) {
nodep->v3warn(SELRANGE,"Selection index out of range: "
<<(nodep->bitp()->castConst()->toSInt()+fromlsb)
<<" outside "<<frommsb<<":"<<fromlsb);
UINFO(1," Related node: "<<nodep<<endl);
}
widthCheckSized(nodep,"Extract Range",nodep->bitp(),selwidthDTypep,EXTEND_EXP,false/*NOWARN*/);
}
}

2
test_regress/t/t_func.v
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@ -41,7 +41,9 @@ module t;
if (vec[0] != 32'h333) $stop;
if (vec[1] != 32'hdef) $stop;
// verilator lint_off SELRANGE
incr(vec[2],vec[0],vec[2]); // Reading/Writing past end of vector!
// verilator lint_on SELRANGE
n=1;
nil();

26
test_regress/t/t_math_const.v
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@ -108,19 +108,19 @@ module t (/*AUTOARG*/
w32 = 12; w32 <<= 1; if (w32 != 24) $stop;
// Increments
v32[2] = 12; v32[2]++; if (v32[2] != 13) $stop;
v32[2] = 12; ++v32[2]; if (v32[2] != 13) $stop;
v32[2] = 12; v32[2]--; if (v32[2] != 11) $stop;
v32[2] = 12; --v32[2]; if (v32[2] != 11) $stop;
v32[2] = 12; v32[2] += 2; if (v32[2] != 14) $stop;
v32[2] = 12; v32[2] -= 2; if (v32[2] != 10) $stop;
v32[2] = 12; v32[2] *= 2; if (v32[2] != 24) $stop;
v32[2] = 12; v32[2] /= 2; if (v32[2] != 6) $stop;
v32[2] = 12; v32[2] &= 6; if (v32[2] != 4) $stop;
v32[2] = 12; v32[2] |= 15; if (v32[2] != 15) $stop;
v32[2] = 12; v32[2] ^= 15; if (v32[2] != 3) $stop;
v32[2] = 12; v32[2] >>= 1; if (v32[2] != 6) $stop;
v32[2] = 12; v32[2] <<= 1; if (v32[2] != 24) $stop;
v32[1] = 12; v32[1]++; if (v32[1] != 13) $stop;
v32[1] = 12; ++v32[1]; if (v32[1] != 13) $stop;
v32[1] = 12; v32[1]--; if (v32[1] != 11) $stop;
v32[1] = 12; --v32[1]; if (v32[1] != 11) $stop;
v32[1] = 12; v32[1] += 2; if (v32[1] != 14) $stop;
v32[1] = 12; v32[1] -= 2; if (v32[1] != 10) $stop;
v32[1] = 12; v32[1] *= 2; if (v32[1] != 24) $stop;
v32[1] = 12; v32[1] /= 2; if (v32[1] != 6) $stop;
v32[1] = 12; v32[1] &= 6; if (v32[1] != 4) $stop;
v32[1] = 12; v32[1] |= 15; if (v32[1] != 15) $stop;
v32[1] = 12; v32[1] ^= 15; if (v32[1] != 3) $stop;
v32[1] = 12; v32[1] >>= 1; if (v32[1] != 6) $stop;
v32[1] = 12; v32[1] <<= 1; if (v32[1] != 24) $stop;
end
if (cyc==2) begin
win <= 32'h123123;

3
test_regress/t/t_mem_first.v
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@ -74,11 +74,12 @@ module t (/*AUTOARG*/
// verilator lint_on width
if (np2_guard[6]!=0 || np2_guard[7]!=0) $stop;
end
// lint_checking BNDMEM OFF
// verilator lint_off SELRANGE
if (np2_mem[6] !== np2_mem[7]) begin
$write("Mem[6]!=Mem[7] during randomize...\n");
//$stop; // Random value, so this can happen
end
// verilator lint_on SELRANGE
//if (np2_mem[8] !== np2_mem[9]) $stop; // Enhancement: Illegal indexes, make sure map to X's
//
vec_wide[32:31] <= 2'b11;

3
test_regress/t/t_mem_slice.v
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@ -98,9 +98,6 @@ module t (/*AUTOARG*/
if (active_command2[3] != 2'b11) begin
$stop;
end
if (active_command3[3][1][2] != 2'b11) begin
$stop;
end
end
end

2
test_regress/t/t_param_array.v
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@ -68,7 +68,7 @@ module t (/*AUTOARG*/);
$display("PINID8 %s", STR_PINID[8]);
if (STR_PINID[1] != "ERR") $stop;
if (STR_PINID[8] != "PA0") $stop;
if (pinout_static_const[0][0] != 0) $stop;
if (pinout_static_const[1][0] != 0) $stop;
$write("*-* All Finished *-*\n");
$finish;
end

21
test_regress/t/t_select_bad_range3.pl Executable file
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@ -0,0 +1,21 @@
#!/usr/bin/perl
if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2003 by Wilson Snyder. This program is free software; you can
# redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
compile (
v_flags2 => ["--lint-only"],
fails=>$Self->{v3},
expect=>
'%Warning-SELRANGE: t/t_select_bad_range3.v:\d+: Selection index out of range: 13 outside 12:10
%Warning-SELRANGE: Use .*
%Error: Exiting due to.*',
);
ok(1);
1;

19
test_regress/t/t_select_bad_range3.v Normal file
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@ -0,0 +1,19 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2015 by Wilson Snyder.
module t (/*AUTOARG*/
// Outputs
outwires,
// Inputs
inwires
);
input [7:0] inwires [12:10];
output wire [7:0] outwires [12:10];
assign outwires[10] = inwires[11];
assign outwires[11] = inwires[12];
assign outwires[12] = inwires[13]; // must be an error here
endmodule