forked from github/verilator
Disable over-sensitive debug dump.
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@ -1181,7 +1181,7 @@ private:
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GateLogicVertex* consumeVertexp
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= dynamic_cast<GateLogicVertex*>(outedgep->top());
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AstNode* consumerp = consumeVertexp->nodep();
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m_graphp->dumpDotFilePrefixed("gate_preelim");
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// if (debug() >= 9) m_graphp->dumpDotFilePrefixed("gate_preelim");
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UINFO(9,
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"elim src vtx" << lvertexp << " node " << lvertexp->nodep() << endl);
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UINFO(9,
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