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Support 'primitive', but not yet 'table'.

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This commit is contained in:
Wilson Snyder 2009-11-20 08:41:28 -05:00
parent 62f707f501
commit e479c8a553
2 changed files with 20 additions and 2 deletions
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4
src/verilog.l
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@ -210,6 +210,7 @@ escid \\[^ \t\f\r\n]+
"endcase" { FL; return yENDCASE; }
"endfunction" { FL; return yENDFUNCTION; }
"endmodule" { FL; return yENDMODULE; }
"endprimitive" { FL; return yENDPRIMITIVE; }
"endspecify" { FL; return yENDSPECIFY; }
"endtask" { FL; return yENDTASK; }
"for" { FL; return yFOR; }
@ -232,6 +233,7 @@ escid \\[^ \t\f\r\n]+
"output" { FL; return yOUTPUT; }
"parameter" { FL; return yPARAMETER; }
"posedge" { FL; return yPOSEDGE; }
"primitive" { FL; return yPRIMITIVE; }
"pulldown" { FL; return yPULLDOWN; }
"pullup" { FL; return yPULLUP; }
"reg" { FL; return yREG; }
@ -265,7 +267,6 @@ escid \\[^ \t\f\r\n]+
/* Generic unsupported warnings */
"cmos" { yyerrorf("Unsupported: Verilog 1995 reserved word not implemented: %s",yytext); }
"deassign" { yyerrorf("Unsupported: Verilog 1995 reserved word not implemented: %s",yytext); }
"endprimitive" { yyerrorf("Unsupported: Verilog 1995 reserved word not implemented: %s",yytext); }
"endtable" { yyerrorf("Unsupported: Verilog 1995 reserved word not implemented: %s",yytext); }
"event" { yyerrorf("Unsupported: Verilog 1995 reserved word not implemented: %s",yytext); }
"force" { yyerrorf("Unsupported: Verilog 1995 reserved word not implemented: %s",yytext); }
@ -277,7 +278,6 @@ escid \\[^ \t\f\r\n]+
"medium" { yyerrorf("Unsupported: Verilog 1995 reserved word not implemented: %s",yytext); }
"nmos" { yyerrorf("Unsupported: Verilog 1995 reserved word not implemented: %s",yytext); }
"pmos" { yyerrorf("Unsupported: Verilog 1995 reserved word not implemented: %s",yytext); }
"primitive" { yyerrorf("Unsupported: Verilog 1995 reserved word not implemented: %s",yytext); }
"pull0" { yyerrorf("Unsupported: Verilog 1995 reserved word not implemented: %s",yytext); }
"pull1" { yyerrorf("Unsupported: Verilog 1995 reserved word not implemented: %s",yytext); }
"rcmos" { yyerrorf("Unsupported: Verilog 1995 reserved word not implemented: %s",yytext); }

18
src/verilog.y
View File

@ -260,6 +260,7 @@ class AstSenTree;
%token<fl> yENDGENERATE "endgenerate"
%token<fl> yENDMODULE "endmodule"
%token<fl> yENDPACKAGE "endpackage"
%token<fl> yENDPRIMITIVE "endprimitive"
%token<fl> yENDPROGRAM "endprogram"
%token<fl> yENDPROPERTY "endproperty"
%token<fl> yENDSPECIFY "endspecify"
@ -293,6 +294,7 @@ class AstSenTree;
%token<fl> yPACKAGE "package"
%token<fl> yPARAMETER "parameter"
%token<fl> yPOSEDGE "posedge"
%token<fl> yPRIMITIVE "primitive"
%token<fl> yPRIORITY "priority"
%token<fl> yPROGRAM "program"
%token<fl> yPROPERTY "property"
@ -629,6 +631,12 @@ module_declaration: // ==IEEE: module_declaration
if ($2) $1->addStmtp($2); if ($3) $1->addStmtp($3);
if ($5) $1->addStmtp($5);
SYMP->popScope($1); }
| udpFront parameter_port_listE portsStarE ';'
module_itemListE yENDPRIMITIVE endLabelE
{ $1->modTrace(false); // Stash for implicit wires, etc
if ($2) $1->addStmtp($2); if ($3) $1->addStmtp($3);
if ($5) $1->addStmtp($5);
SYMP->popScope($1); }
//
//UNSUP yEXTERN modFront parameter_port_listE portsStarE ';'
//UNSUP { UNSUP }
@ -644,6 +652,16 @@ modFront<modulep>:
SYMP->pushNew($$); }
;
udpFront<modulep>:
yPRIMITIVE lifetimeE idAny
{ $$ = new AstModule($1,*$3); $$->inLibrary(true);
$$->modTrace(false);
$$->addStmtp(new AstPragma($1,AstPragmaType::INLINE_MODULE));
PARSEP->fileline()->tracingOn(false);
PARSEP->rootp()->addModulep($$);
SYMP->pushNew($$); }
;
parameter_value_assignmentE<pinp>: // IEEE: [ parameter_value_assignment ]
/* empty */ { $$ = NULL; }
| '#' '(' cellpinList ')' { $$ = $3; }