Tests: Use vl_time_stamp64 where reasonable

bin/verilator

@@ -5250,7 +5250,7 @@ want all data to land in the same output file.
         topp->trace(tfp, 99);  // Trace 99 levels of hierarchy
         tfp->open("obj_dir/t_trace_ena_cc/simx.vcd");
         ...
-        while (sc_time_stamp() < sim_time && !Verilated::gotFinish()) {
+        while (vl_time_stamp64() < sim_time && !Verilated::gotFinish()) {
             main_time += #;
             tfp->dump(main_time);
         }

include/verilated_vcd_sc.h

@@ -53,7 +53,7 @@ public:
     // METHODS
     /// Called by SystemC simulate()
     virtual void cycle(bool delta_cycle) {
-        if (!delta_cycle) { this->dump(sc_time_stamp().to_double()); }
+        if (!delta_cycle) this->dump(sc_time_stamp().to_double());
     }
 
 private:

test_regress/driver.pl

@@ -1737,7 +1737,7 @@ sub _make_main {
     if (!$self->sc) {
         if ($self->{vl_time_stamp64}) {
             print $fh "vluint64_t main_time = 0;\n";
-            print $fh "vluint64_t vl_time_stamp() { return main_time; }\n";
+            print $fh "vluint64_t vl_time_stamp64() { return main_time; }\n";
         } else {
             print $fh "double main_time = 0;\n";
             print $fh "double sc_time_stamp() { return main_time; }\n";

test_regress/t/t_clk_inp_init.cpp

@@ -14,7 +14,7 @@ vluint64_t main_time;
 double sc_time_stamp() { return main_time; }
 
 void oneTest(int seed) {
-    double sim_time = 1000;
+    vluint64_t sim_time = 1000;
 
 #ifdef TEST_VERBOSE
     VL_PRINTF("== Seed=%d\n", seed);
@@ -33,7 +33,7 @@ void oneTest(int seed) {
     topp->eval();
 
     // Tick for a little bit
-    while (sc_time_stamp() < sim_time && !Verilated::gotFinish()) {
+    while (vl_time_stamp64() < sim_time && !Verilated::gotFinish()) {
         topp->clk = 0;
         topp->eval();
 

test_regress/t/t_dpi_var.cpp

@@ -114,7 +114,7 @@ unsigned int main_time = 0;
 
 double sc_time_stamp() { return main_time; }
 int main(int argc, char** argv, char** env) {
-    double sim_time = 1100;
+    vluint64_t sim_time = 1100;
     Verilated::commandArgs(argc, argv);
     Verilated::debug(0);
 
@@ -132,7 +132,7 @@ int main(int argc, char** argv, char** env) {
     topp->clk = 0;
     main_time += 10;
 
-    while (sc_time_stamp() < sim_time && !Verilated::gotFinish()) {
+    while (vl_time_stamp64() < sim_time && !Verilated::gotFinish()) {
         main_time += 1;
         topp->eval();
         topp->clk = !topp->clk;

test_regress/t/t_trace_two_cc.cpp

@@ -33,7 +33,7 @@ vluint64_t main_time = 0;
 double sc_time_stamp() { return main_time; }
 
 int main(int argc, char** argv, char** env) {
-    double sim_time = 1100;
+    vluint64_t sim_time = 1100;
     Verilated::commandArgs(argc, argv);
     Verilated::debug(0);
     Verilated::traceEverOn(true);
@@ -70,7 +70,7 @@ int main(int argc, char** argv, char** env) {
         ap->clk = false;
         main_time += 10;
     }
-    while (sc_time_stamp() < sim_time && !Verilated::gotFinish()) {
+    while (vl_time_stamp64() < sim_time && !Verilated::gotFinish()) {
         ap->clk = !ap->clk;
         bp->clk = ap->clk;
         ap->eval_step();

test_regress/t/t_vpi_cb_iter.cpp

@@ -169,7 +169,7 @@ static void register_filler_cb() {
 double sc_time_stamp() { return main_time; }
 
 int main(int argc, char** argv, char** env) {
-    double sim_time = 100;
+    vluint64_t sim_time = 100;
     Verilated::commandArgs(argc, argv);
     Verilated::debug(0);
 
@@ -184,7 +184,7 @@ int main(int argc, char** argv, char** env) {
     topp->eval();
     topp->clk = 0;
 
-    while (sc_time_stamp() < sim_time && !Verilated::gotFinish()) {
+    while (vl_time_stamp64() < sim_time && !Verilated::gotFinish()) {
         main_time += 1;
         if (verbose) { VL_PRINTF("Sim Time %d got_error %d\n", main_time, got_error); }
         topp->clk = !topp->clk;

test_regress/t/t_vpi_cbs_called.cpp

@@ -248,7 +248,7 @@ static int register_test_callback() {
 double sc_time_stamp() { return main_time; }
 
 int main(int argc, char** argv, char** env) {
-    double sim_time = 100;
+    vluint64_t sim_time = 100;
     bool cbs_called;
     Verilated::commandArgs(argc, argv);
 
@@ -262,7 +262,7 @@ int main(int argc, char** argv, char** env) {
     topp->clk = 0;
     main_time += 1;
 
-    while (sc_time_stamp() < sim_time && !Verilated::gotFinish()) {
+    while (vl_time_stamp64() < sim_time && !Verilated::gotFinish()) {
         if (verbose) {
             VL_PRINTF("-- { Sim Time %d , Callback %s (%d) , Testcase State %d } --\n", main_time,
                       cb_reason_to_string(*cb_iter), *cb_iter, *state_iter);

test_regress/t/t_vpi_get.cpp

@@ -234,7 +234,7 @@ void (*vlog_startup_routines[])() = {vpi_compat_bootstrap, 0};
 #else
 double sc_time_stamp() { return main_time; }
 int main(int argc, char** argv, char** env) {
-    double sim_time = 1100;
+    vluint64_t sim_time = 1100;
     Verilated::commandArgs(argc, argv);
     Verilated::debug(0);
 
@@ -258,7 +258,7 @@ int main(int argc, char** argv, char** env) {
     topp->clk = 0;
     main_time += 10;
 
-    while (sc_time_stamp() < sim_time && !Verilated::gotFinish()) {
+    while (vl_time_stamp64() < sim_time && !Verilated::gotFinish()) {
         main_time += 1;
         topp->eval();
         VerilatedVpi::callValueCbs();

test_regress/t/t_vpi_memory.cpp

@@ -245,7 +245,7 @@ void (*vlog_startup_routines[])() = {vpi_compat_bootstrap, 0};
 
 double sc_time_stamp() { return main_time; }
 int main(int argc, char** argv, char** env) {
-    double sim_time = 1100;
+    vluint64_t sim_time = 1100;
     Verilated::commandArgs(argc, argv);
     Verilated::debug(0);
     // we're going to be checking for these errors do don't crash out
@@ -271,7 +271,7 @@ int main(int argc, char** argv, char** env) {
     topp->clk = 0;
     main_time += 10;
 
-    while (sc_time_stamp() < sim_time && !Verilated::gotFinish()) {
+    while (vl_time_stamp64() < sim_time && !Verilated::gotFinish()) {
         main_time += 1;
         topp->eval();
         VerilatedVpi::callValueCbs();

test_regress/t/t_vpi_module.cpp

@@ -171,7 +171,7 @@ void (*vlog_startup_routines[])() = {vpi_compat_bootstrap, 0};
 
 double sc_time_stamp() { return main_time; }
 int main(int argc, char** argv, char** env) {
-    double sim_time = 1100;
+    vluint64_t sim_time = 1100;
     Verilated::commandArgs(argc, argv);
     Verilated::debug(0);
     // we're going to be checking for these errors do don't crash out
@@ -200,7 +200,7 @@ int main(int argc, char** argv, char** env) {
     topp->clk = 0;
     main_time += 10;
 
-    while (sc_time_stamp() < sim_time && !Verilated::gotFinish()) {
+    while (vl_time_stamp64() < sim_time && !Verilated::gotFinish()) {
         main_time += 1;
         topp->eval();
         VerilatedVpi::callValueCbs();

test_regress/t/t_vpi_param.cpp

@@ -242,7 +242,7 @@ void (*vlog_startup_routines[])() = {vpi_compat_bootstrap, 0};
 
 double sc_time_stamp() { return main_time; }
 int main(int argc, char** argv, char** env) {
-    double sim_time = 1100;
+    vluint64_t sim_time = 1100;
     Verilated::commandArgs(argc, argv);
     Verilated::debug(0);
     // we're going to be checking for these errors do don't crash out
@@ -268,7 +268,7 @@ int main(int argc, char** argv, char** env) {
     topp->clk = 0;
     main_time += 10;
 
-    while (sc_time_stamp() < sim_time && !Verilated::gotFinish()) {
+    while (vl_time_stamp64() < sim_time && !Verilated::gotFinish()) {
         main_time += 1;
         topp->eval();
         VerilatedVpi::callValueCbs();

test_regress/t/t_vpi_time_cb.cpp

@@ -193,7 +193,7 @@ void (*vlog_startup_routines[])() = {vpi_compat_bootstrap, 0};
 double sc_time_stamp() { return main_time; }
 
 int main(int argc, char** argv, char** env) {
-    double sim_time = 1100;
+    vluint64_t sim_time = 1100;
     Verilated::commandArgs(argc, argv);
     Verilated::debug(0);
 
@@ -233,7 +233,7 @@ int main(int argc, char** argv, char** env) {
     topp->clk = 0;
     main_time += 1;
 
-    while (sc_time_stamp() < sim_time && !Verilated::gotFinish()) {
+    while (vl_time_stamp64() < sim_time && !Verilated::gotFinish()) {
         main_time += 1;
         topp->eval();
         VerilatedVpi::callValueCbs();

test_regress/t/t_vpi_unimpl.cpp

@@ -186,7 +186,7 @@ int mon_check() {
 
 double sc_time_stamp() { return main_time; }
 int main(int argc, char** argv, char** env) {
-    double sim_time = 1100;
+    vluint64_t sim_time = 1100;
     Verilated::commandArgs(argc, argv);
     Verilated::debug(0);
     // we're going to be checking for these errors do don't crash out
@@ -212,7 +212,7 @@ int main(int argc, char** argv, char** env) {
     topp->clk = 0;
     main_time += 10;
 
-    while (sc_time_stamp() < sim_time && !Verilated::gotFinish()) {
+    while (vl_time_stamp64() < sim_time && !Verilated::gotFinish()) {
         main_time += 1;
         topp->eval();
         // VerilatedVpi::callValueCbs();   // Make sure can link without verilated_vpi.h included

test_regress/t/t_vpi_var.cpp

@@ -686,7 +686,7 @@ void (*vlog_startup_routines[])() = {vpi_compat_bootstrap, 0};
 
 double sc_time_stamp() { return main_time; }
 int main(int argc, char** argv, char** env) {
-    double sim_time = 1100;
+    vluint64_t sim_time = 1100;
     Verilated::commandArgs(argc, argv);
     Verilated::debug(0);
 
@@ -710,7 +710,7 @@ int main(int argc, char** argv, char** env) {
     topp->clk = 0;
     main_time += 10;
 
-    while (sc_time_stamp() < sim_time && !Verilated::gotFinish()) {
+    while (vl_time_stamp64() < sim_time && !Verilated::gotFinish()) {
         main_time += 1;
         topp->eval();
         VerilatedVpi::callValueCbs();

test_regress/t/t_vpi_zero_time_cb.cpp

@@ -116,7 +116,7 @@ void (*vlog_startup_routines[])() = {vpi_compat_bootstrap, 0};
 double sc_time_stamp() { return main_time; }
 
 int main(int argc, char** argv, char** env) {
-    double sim_time = 1100;
+    vluint64_t sim_time = 1100;
     Verilated::commandArgs(argc, argv);
     Verilated::debug(0);
 
@@ -156,7 +156,7 @@ int main(int argc, char** argv, char** env) {
     topp->clk = 0;
     main_time += 1;
 
-    while (sc_time_stamp() < sim_time && !Verilated::gotFinish()) {
+    while (vl_time_stamp64() < sim_time && !Verilated::gotFinish()) {
         main_time += 1;
         topp->eval();
         VerilatedVpi::callValueCbs();