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Fix default clocking syntax; covers go outside the block

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Wilson Snyder 2008-08-06 17:51:36 -04:00
parent 3463080a71
commit df107628c6
4 changed files with 19 additions and 22 deletions
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23
src/V3AssertPre.cpp
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@ -56,8 +56,12 @@ private:
// Return NULL for always
AstSenTree* newp = NULL;
AstSenItem* senip = m_senip ? m_senip : m_seniDefaultp;
if (senip) newp = new AstSenTree(nodep->fileline(), senip->cloneTree(true));
if (!senip) nodep->v3error("Unsupported: Unclocked assertion");
if (!senip) {
nodep->v3error("Unsupported: Unclocked assertion");
newp = new AstSenTree(nodep->fileline(), NULL);
} else {
newp = new AstSenTree(nodep->fileline(), senip->cloneTree(true));
}
return newp;
}
void clearAssertInfo() {
@ -75,15 +79,14 @@ private:
}
virtual void visit(AstClocking* nodep, AstNUser*) {
UINFO(8," CLOCKING"<<nodep<<endl);
AstSenItem* lastp = m_seniDefaultp;
{
// Store the new default clock only in this scope
m_seniDefaultp = nodep->sensesp();
nodep->iterateChildren(*this);
// Store the new default clock, reset on new module
m_seniDefaultp = nodep->sensesp();
// Trash it, keeping children
if (nodep->bodysp()) {
nodep->replaceWith(nodep->bodysp()->unlinkFrBack());
} else {
nodep->unlinkFrBack();
}
m_seniDefaultp = lastp;
// Trash it
nodep->replaceWith(nodep->bodysp()->unlinkFrBack());
pushDeletep(nodep); nodep=NULL;
}

2
src/bisonpre
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@ -169,7 +169,7 @@ sub warning_check {
my $fh = IO::File->new("<$filename") or die "%Error: $! $filename\n";
while (defined(my $line = $fh->getline)) {
if ($line =~ /conflicts/) {
if ($line =~ /(conflicts|warning:)/) {
clean_output();
die "%Error: $filename:$.: $line\n";
}

11
src/verilog.y
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@ -1431,13 +1431,8 @@ labeledStmt<nodep>:
;
clocking_declaration<nodep>: // IEEE: clocking_declaration (INCOMPLETE)
yDEFAULT yCLOCKING '@' '(' senitemEdge ')' ';' clocking_item yENDCLOCKING
{ $$ = new AstClocking($1, $5, $8); }
;
clocking_item<nodep>: // IEEE: clocking_item (INCOMPLETE)
concurrent_assertion_item { $$ = $1; }
| clocking_item concurrent_assertion_item { $$ = $1->addNext($2); }
yDEFAULT yCLOCKING '@' '(' senitemEdge ')' ';' yENDCLOCKING
{ $$ = new AstClocking($1, $5, NULL); }
;
concurrent_assertion_item<nodep>: // IEEE: concurrent_assertion_item (complete)
@ -1490,7 +1485,7 @@ pslDirOne<nodep>:
;
pslDecl<nodep>:
yDEFAULT yPSL_CLOCK '=' senitemEdge ';' { $$ = new AstPslDefClock($3, $4); }
yDEFAULT yPSL_CLOCK '=' senitemEdge ';' { $$ = new AstPslDefClock($3, $4); UINFO(0,"CRE "<<$$<<endl)}
| yDEFAULT yPSL_CLOCK '=' '(' senitemEdge ')' ';' { $$ = new AstPslDefClock($3, $5); }
;

5
test_regress/t/t_assert_cover.v
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@ -54,9 +54,8 @@ module Test
cover property (@(posedge clk) cyc==5) $display("*COVER: Cyc==5");
// Using default clock
default clocking @(posedge clk);
cover property (cyc==6) $display("*COVER: Cyc==6");
endclocking
default clocking @(posedge clk); endclocking
cover property (cyc==6) $display("*COVER: Cyc==6");
// Disable statement
// Note () after disable are required