Internals: Parse interconnect then say unsupported

src/verilog.l

@@ -621,7 +621,7 @@ vnum    {vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5}
 <S12,S17,SAX>{
   /*     Keywords */
   "implements"          { FL; return yIMPLEMENTS; }
-  "interconnect"        { ERROR_RSVD_WORD("SystemVerilog 2012"); }
+  "interconnect"        { FL; return yINTERCONNECT; }
   "nettype"             { ERROR_RSVD_WORD("SystemVerilog 2012"); }
   "soft"                { FL; return ySOFT; }
 }

src/verilog.y

@@ -358,7 +358,7 @@ int V3ParseGrammar::s_modTypeImpNum = 0;
 // Apply a strength to a list of nodes under beginp
 #define STRENGTH_LIST(beginp, strengthSpecNodep, typeToCast) \
     { \
-        if (AstStrengthSpec* specp = VN_CAST(strengthSpecNodep, StrengthSpec)) { \
+        if (AstStrengthSpec* const specp = VN_CAST(strengthSpecNodep, StrengthSpec)) { \
             for (auto* nodep = beginp; nodep; nodep = nodep->nextp()) { \
                 auto* const assignp = VN_AS(nodep, typeToCast); \
                 assignp->strengthSpecp(nodep == beginp ? specp : specp->cloneTree(false)); \
@@ -643,7 +643,7 @@ BISONPRE_VERSION(3.7,%define api.header.include {"V3ParseBison.h"})
 %token<fl>              yINSIDE         "inside"
 %token<fl>              yINT            "int"
 %token<fl>              yINTEGER        "integer"
-//UNSUP %token<fl>      yINTERCONNECT   "interconnect"
+%token<fl>              yINTERCONNECT   "interconnect"
 %token<fl>              yINTERFACE      "interface"
 //UNSUP %token<fl>      yINTERSECT      "intersect"
 %token<fl>              yJOIN           "join"
@@ -1507,6 +1507,14 @@ port<nodep>:                    // ==IEEE: port
         |       portDirNetE yINTERFACE      '.' idAny/*modport*/ portSig rangeListE sigAttrListE
                         { $$ = nullptr; BBUNSUP($<fl>2, "Unsupported: generic interfaces"); }
         //
+        |       portDirNetE yINTERCONNECT signingE rangeListE portSig variable_dimensionListE sigAttrListE
+                        { $$ = $5;
+                          BBUNSUP($<fl>2, "Unsupported: interconnect");
+                          AstNodeDType* const dtp = GRAMMARP->addRange(
+                                    new AstBasicDType{$2, LOGIC_IMPLICIT, $3}, $4, true);
+                          VARDTYPE(dtp);
+                          addNextNull($$, VARDONEP($$, $6, $7)); }
+        //
         //                      // IEEE: ansi_port_declaration, with [port_direction] removed
         //                      //   IEEE: [ net_port_header | interface_port_header ]
         //                      //         port_identifier { unpacked_dimension } [ '=' constant_expression ]
@@ -1905,7 +1913,12 @@ net_declarationFront:           // IEEE: beginning of net_declaration
                         { VARDTYPE_NDECL($5);
                           GRAMMARP->setNetStrength(VN_CAST($3, StrengthSpec));
                         }
-        //UNSUP net_declRESET yINTERCONNECT signingE rangeListE { VARNET($2); VARDTYPE(x); }
+        |       net_declRESET yINTERCONNECT signingE rangeListE
+                        { BBUNSUP($<fl>2, "Unsupported: interconnect");
+                          VARDECL(WIRE);
+                          AstNodeDType* const dtp = GRAMMARP->addRange(
+                                    new AstBasicDType{$2, LOGIC_IMPLICIT, $3}, $4, true);
+                          VARDTYPE_NDECL(dtp); }
         ;
 
 net_declRESET:

test_regress/t/t_interconnect.out

@@ -0,0 +1,14 @@
+%Error-UNSUPPORTED: t/t_interconnect.v:12:4: Unsupported: interconnect
+   12 |    interconnect a;
+      |    ^~~~~~~~~~~~
+                    ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest
+%Error-UNSUPPORTED: t/t_interconnect.v:13:4: Unsupported: interconnect
+   13 |    interconnect b;
+      |    ^~~~~~~~~~~~
+%Error-UNSUPPORTED: t/t_interconnect.v:22:11: Unsupported: interconnect
+   22 |    output interconnect a,
+      |           ^~~~~~~~~~~~
+%Error-UNSUPPORTED: t/t_interconnect.v:23:11: Unsupported: interconnect
+   23 |    output interconnect b);
+      |           ^~~~~~~~~~~~
+%Error: Exiting due to

test_regress/t/t_interconnect.pl

@@ -0,0 +1,20 @@
+#!/usr/bin/env perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+scenarios(simulator => 1);
+
+compile(
+    verilator_flags2 => ["--timing"],
+    fails => $Self->{vlt_all},
+    expect_filename => $Self->{golden_filename},
+    );
+
+ok(1);
+1;

test_regress/t/t_interconnect.v

@@ -0,0 +1,49 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2023 by Wilson Snyder.
+// SPDX-License-Identifier: CC0-1.0
+
+// Note: Other simulator's support for interconnect seems rare, the below might
+// not be correct code.
+
+module t(/*AUTOARG*/);
+
+   interconnect a;
+   interconnect b;
+
+   moda suba (.a, .b);
+   modb #(.TA_t(real)) subb (.a(a), .b(b));
+
+endmodule
+
+module moda
+  (
+   output interconnect a,
+   output interconnect b);
+   modaa subaa (.a, .b);
+endmodule
+
+module modaa
+  (
+   output real a,
+   output int  b);
+   initial begin
+      a = 1.234;
+      b = 1234;
+   end
+endmodule
+
+module modb
+  #(parameter type TA_t = int)
+  (
+   input TA_t a,
+   input int b);
+   initial begin
+      #10;
+      if (a != 1.234) $stop;
+      if (b != 1234) $stop;
+      $write("*-* All Finished *-*\n");
+      $finish;
+   end
+endmodule

test_regress/t/t_interconnect_bad.out

@@ -0,0 +1,5 @@
+%Error-UNSUPPORTED: t/t_interconnect_bad.v:9:4: Unsupported: interconnect
+    9 |    interconnect a;
+      |    ^~~~~~~~~~~~
+                    ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest
+%Error: Exiting due to

test_regress/t/t_interconnect_bad.pl

@@ -0,0 +1,19 @@
+#!/usr/bin/env perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+scenarios(simulator => 1);
+
+compile(
+    fails => 1,
+    expect_filename => $Self->{golden_filename},
+    );
+
+ok(1);
+1;

test_regress/t/t_interconnect_bad.v

@@ -0,0 +1,17 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2023 by Wilson Snyder.
+// SPDX-License-Identifier: CC0-1.0
+
+module t(/*AUTOARG*/);
+
+   interconnect a;
+
+   assign a = 1; // Bad IEEE 6.6.8 - shall not be used in continuous assignment
+
+   initial begin
+      a = 2; // Bad IEEE 6.6.8 - shall not be used in procedural assignment
+   end
+
+endmodule