forked from github/verilator
Internals: Parse interconnect then say unsupported
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@ -621,7 +621,7 @@ vnum {vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5}
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<S12,S17,SAX>{
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/* Keywords */
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"implements" { FL; return yIMPLEMENTS; }
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"interconnect" { ERROR_RSVD_WORD("SystemVerilog 2012"); }
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"interconnect" { FL; return yINTERCONNECT; }
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"nettype" { ERROR_RSVD_WORD("SystemVerilog 2012"); }
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"soft" { FL; return ySOFT; }
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}
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@ -358,7 +358,7 @@ int V3ParseGrammar::s_modTypeImpNum = 0;
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// Apply a strength to a list of nodes under beginp
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#define STRENGTH_LIST(beginp, strengthSpecNodep, typeToCast) \
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{ \
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if (AstStrengthSpec* specp = VN_CAST(strengthSpecNodep, StrengthSpec)) { \
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if (AstStrengthSpec* const specp = VN_CAST(strengthSpecNodep, StrengthSpec)) { \
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for (auto* nodep = beginp; nodep; nodep = nodep->nextp()) { \
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auto* const assignp = VN_AS(nodep, typeToCast); \
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assignp->strengthSpecp(nodep == beginp ? specp : specp->cloneTree(false)); \
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@ -643,7 +643,7 @@ BISONPRE_VERSION(3.7,%define api.header.include {"V3ParseBison.h"})
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%token<fl> yINSIDE "inside"
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%token<fl> yINT "int"
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%token<fl> yINTEGER "integer"
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//UNSUP %token<fl> yINTERCONNECT "interconnect"
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%token<fl> yINTERCONNECT "interconnect"
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%token<fl> yINTERFACE "interface"
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//UNSUP %token<fl> yINTERSECT "intersect"
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%token<fl> yJOIN "join"
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@ -1507,6 +1507,14 @@ port<nodep>: // ==IEEE: port
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| portDirNetE yINTERFACE '.' idAny/*modport*/ portSig rangeListE sigAttrListE
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{ $$ = nullptr; BBUNSUP($<fl>2, "Unsupported: generic interfaces"); }
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//
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| portDirNetE yINTERCONNECT signingE rangeListE portSig variable_dimensionListE sigAttrListE
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{ $$ = $5;
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BBUNSUP($<fl>2, "Unsupported: interconnect");
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AstNodeDType* const dtp = GRAMMARP->addRange(
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new AstBasicDType{$2, LOGIC_IMPLICIT, $3}, $4, true);
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VARDTYPE(dtp);
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addNextNull($$, VARDONEP($$, $6, $7)); }
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//
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// // IEEE: ansi_port_declaration, with [port_direction] removed
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// // IEEE: [ net_port_header | interface_port_header ]
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// // port_identifier { unpacked_dimension } [ '=' constant_expression ]
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@ -1905,7 +1913,12 @@ net_declarationFront: // IEEE: beginning of net_declaration
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{ VARDTYPE_NDECL($5);
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GRAMMARP->setNetStrength(VN_CAST($3, StrengthSpec));
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}
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//UNSUP net_declRESET yINTERCONNECT signingE rangeListE { VARNET($2); VARDTYPE(x); }
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| net_declRESET yINTERCONNECT signingE rangeListE
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{ BBUNSUP($<fl>2, "Unsupported: interconnect");
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VARDECL(WIRE);
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AstNodeDType* const dtp = GRAMMARP->addRange(
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new AstBasicDType{$2, LOGIC_IMPLICIT, $3}, $4, true);
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VARDTYPE_NDECL(dtp); }
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;
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net_declRESET:
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14
test_regress/t/t_interconnect.out
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14
test_regress/t/t_interconnect.out
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@ -0,0 +1,14 @@
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%Error-UNSUPPORTED: t/t_interconnect.v:12:4: Unsupported: interconnect
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12 | interconnect a;
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| ^~~~~~~~~~~~
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... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest
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%Error-UNSUPPORTED: t/t_interconnect.v:13:4: Unsupported: interconnect
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13 | interconnect b;
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| ^~~~~~~~~~~~
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%Error-UNSUPPORTED: t/t_interconnect.v:22:11: Unsupported: interconnect
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22 | output interconnect a,
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| ^~~~~~~~~~~~
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%Error-UNSUPPORTED: t/t_interconnect.v:23:11: Unsupported: interconnect
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23 | output interconnect b);
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| ^~~~~~~~~~~~
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%Error: Exiting due to
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20
test_regress/t/t_interconnect.pl
Executable file
20
test_regress/t/t_interconnect.pl
Executable file
@ -0,0 +1,20 @@
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#!/usr/bin/env perl
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if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
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# DESCRIPTION: Verilator: Verilog Test driver/expect definition
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#
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# Copyright 2003 by Wilson Snyder. This program is free software; you
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# can redistribute it and/or modify it under the terms of either the GNU
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# Lesser General Public License Version 3 or the Perl Artistic License
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# Version 2.0.
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# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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scenarios(simulator => 1);
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compile(
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verilator_flags2 => ["--timing"],
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fails => $Self->{vlt_all},
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expect_filename => $Self->{golden_filename},
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);
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ok(1);
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1;
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49
test_regress/t/t_interconnect.v
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49
test_regress/t/t_interconnect.v
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@ -0,0 +1,49 @@
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2023 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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// Note: Other simulator's support for interconnect seems rare, the below might
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// not be correct code.
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module t(/*AUTOARG*/);
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interconnect a;
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interconnect b;
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moda suba (.a, .b);
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modb #(.TA_t(real)) subb (.a(a), .b(b));
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endmodule
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module moda
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(
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output interconnect a,
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output interconnect b);
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modaa subaa (.a, .b);
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endmodule
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module modaa
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(
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output real a,
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output int b);
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initial begin
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a = 1.234;
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b = 1234;
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end
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endmodule
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module modb
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#(parameter type TA_t = int)
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(
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input TA_t a,
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input int b);
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initial begin
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#10;
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if (a != 1.234) $stop;
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if (b != 1234) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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5
test_regress/t/t_interconnect_bad.out
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5
test_regress/t/t_interconnect_bad.out
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@ -0,0 +1,5 @@
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%Error-UNSUPPORTED: t/t_interconnect_bad.v:9:4: Unsupported: interconnect
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9 | interconnect a;
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| ^~~~~~~~~~~~
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... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest
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%Error: Exiting due to
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19
test_regress/t/t_interconnect_bad.pl
Executable file
19
test_regress/t/t_interconnect_bad.pl
Executable file
@ -0,0 +1,19 @@
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#!/usr/bin/env perl
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if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
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# DESCRIPTION: Verilator: Verilog Test driver/expect definition
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#
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# Copyright 2003 by Wilson Snyder. This program is free software; you
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# can redistribute it and/or modify it under the terms of either the GNU
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# Lesser General Public License Version 3 or the Perl Artistic License
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# Version 2.0.
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# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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scenarios(simulator => 1);
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compile(
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fails => 1,
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expect_filename => $Self->{golden_filename},
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);
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ok(1);
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1;
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17
test_regress/t/t_interconnect_bad.v
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17
test_regress/t/t_interconnect_bad.v
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@ -0,0 +1,17 @@
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2023 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t(/*AUTOARG*/);
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interconnect a;
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assign a = 1; // Bad IEEE 6.6.8 - shall not be used in continuous assignment
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initial begin
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a = 2; // Bad IEEE 6.6.8 - shall not be used in procedural assignment
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end
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endmodule
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