diff --git a/test_regress/t/t_interface_param_loop_bad.pl b/test_regress/t/t_interface_param_loop_bad.pl
new file mode 100755
index 000000000..2cd34c191
--- /dev/null
+++ b/test_regress/t/t_interface_param_loop_bad.pl
@@ -0,0 +1,20 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2019 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+
+$Self->{vlt_all} and unsupported("Verilator unsupported, bug1626");
+
+scenarios(simulator => 1);
+
+compile(
+    fails => 1,
+    expect_filename => $Self->{golden_filename},
+    );
+
+ok(1);
+1;
diff --git a/test_regress/t/t_interface_param_loop_bad.v b/test_regress/t/t_interface_param_loop_bad.v
new file mode 100644
index 000000000..5a9fe1691
--- /dev/null
+++ b/test_regress/t/t_interface_param_loop_bad.v
@@ -0,0 +1,22 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2019 by Johan Bjork.
+
+module t ();
+   simple_bus #(.WIDTH(simple.get_width()))  sb_intf();
+   simple_bus #(.WIDTH(sb_intf.get_width())) simple();
+
+   initial begin
+      $write("*-* All Finished *-*\n");
+      $finish;
+   end
+endmodule
+
+interface simple_bus #(parameter int WIDTH = 8);
+   logic [WIDTH-1:0] data;
+
+   function automatic int get_width();
+      return WIDTH;
+   endfunction
+endinterface