forked from github/verilator
Parse checkers as UNSUPPORTED.
This commit is contained in:
Wilson Snyder
parent
e9441cff50
commit
d9c4d9316f
@ -461,6 +461,10 @@ chandle
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Treated as a "longint"; does not yet warn about operations specified as
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illegal on chandles.
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checker
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Treated as a "module"; does not yet warn about many constructs illegal
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inside a checker.
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disable
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Disable statements may be used only if the block being disabled is a
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block the disable statement itself is inside. This was commonly used to
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@ -594,8 +594,8 @@ vnum {vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5}
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<S09,S12,S17,SAX>{
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/* Keywords */
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"accept_on" { ERROR_RSVD_WORD("SystemVerilog 2009"); }
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"checker" { ERROR_RSVD_WORD("SystemVerilog 2009"); }
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"endchecker" { ERROR_RSVD_WORD("SystemVerilog 2009"); }
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"checker" { FL; return yCHECKER; }
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"endchecker" { FL; return yENDCHECKER; }
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"eventually" { ERROR_RSVD_WORD("SystemVerilog 2009"); }
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"global" { FL; return yGLOBAL__LEX; }
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"implies" { ERROR_RSVD_WORD("SystemVerilog 2009"); }
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232
src/verilog.y
232
src/verilog.y
@ -562,7 +562,7 @@ BISONPRE_VERSION(3.7,%define api.header.include {"V3ParseBison.h"})
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%token<fl> yCASEX "casex"
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%token<fl> yCASEZ "casez"
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%token<fl> yCHANDLE "chandle"
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//UNSUP %token<fl> yCHECKER "checker"
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%token<fl> yCHECKER "checker"
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%token<fl> yCLASS "class"
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//UNSUP %token<fl> yCLOCK "clock"
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%token<fl> yCLOCKING "clocking"
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@ -588,7 +588,7 @@ BISONPRE_VERSION(3.7,%define api.header.include {"V3ParseBison.h"})
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%token<fl> yELSE "else"
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%token<fl> yEND "end"
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%token<fl> yENDCASE "endcase"
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//UNSUP %token<fl> yENDCHECKER "endchecker"
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%token<fl> yENDCHECKER "endchecker"
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%token<fl> yENDCLASS "endclass"
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%token<fl> yENDCLOCKING "endclocking"
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%token<fl> yENDFUNCTION "endfunction"
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@ -1261,7 +1261,7 @@ package_or_generate_item_declaration<nodep>: // ==IEEE: package_or_generate_i
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| data_declaration { $$ = $1; }
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| task_declaration { $$ = $1; }
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| function_declaration { $$ = $1; }
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//UNSUP checker_declaration { $$ = $1; }
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| checker_declaration { $$ = $1; }
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| dpi_import_export { $$ = $1; }
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| extern_constraint_declaration { $$ = $1; }
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| class_declaration { $$ = $1; }
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@ -2610,13 +2610,7 @@ module_common_item<nodep>: // ==IEEE: module_common_item
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{ $$ = nullptr; BBUNSUP($1, "Unsupported: alias statements"); }
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| initial_construct { $$ = $1; }
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| final_construct { $$ = $1; }
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// // IEEE: always_construct
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// // Verilator only - event_control attached to always
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| yALWAYS stmtBlock { $$ = new AstAlways{$1, VAlwaysKwd::ALWAYS, nullptr, $2}; }
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| yALWAYS_FF stmtBlock { $$ = new AstAlways{$1, VAlwaysKwd::ALWAYS_FF, nullptr, $2}; }
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| yALWAYS_LATCH stmtBlock { $$ = new AstAlways{$1, VAlwaysKwd::ALWAYS_LATCH, nullptr, $2}; }
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| yALWAYS_COMB stmtBlock { $$ = new AstAlways{$1, VAlwaysKwd::ALWAYS_COMB, nullptr, $2}; }
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//
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| always_construct { $$ = $1; }
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| loop_generate_construct { $$ = $1; }
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| conditional_generate_construct { $$ = $1; }
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| elaboration_system_task { $$ = $1; }
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@ -2625,6 +2619,14 @@ module_common_item<nodep>: // ==IEEE: module_common_item
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| error ';' { $$ = nullptr; }
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;
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always_construct<nodep>: // IEEE: == always_construct
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// // Verilator only - event_control attached to always
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yALWAYS stmtBlock { $$ = new AstAlways{$1, VAlwaysKwd::ALWAYS, nullptr, $2}; }
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| yALWAYS_FF stmtBlock { $$ = new AstAlways{$1, VAlwaysKwd::ALWAYS_FF, nullptr, $2}; }
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| yALWAYS_LATCH stmtBlock { $$ = new AstAlways{$1, VAlwaysKwd::ALWAYS_LATCH, nullptr, $2}; }
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| yALWAYS_COMB stmtBlock { $$ = new AstAlways{$1, VAlwaysKwd::ALWAYS_COMB, nullptr, $2}; }
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;
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continuous_assign<nodep>: // IEEE: continuous_assign
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yASSIGN driveStrengthE delay_controlE assignList ';'
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{
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@ -2697,17 +2699,21 @@ generate_region<nodep>: // ==IEEE: generate_region
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| yGENERATE yENDGENERATE { $$ = nullptr; }
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;
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//UNSUPc_generate_region<nodep>: // IEEE: generate_region (for checkers)
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//UNSUP BISONPRE_COPY(generate_region,{s/~c~/c_/g}) // {copied}
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//UNSUP ;
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c_generate_region<nodep>: // IEEE: generate_region (for checkers)
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BISONPRE_COPY(generate_region,{s/~c~/c_/g}) // {copied}
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;
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generate_block_or_null<nodep>: // IEEE: generate_block_or_null (called from gencase/genif/genfor)
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// ';' // is included in
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// // IEEE: generate_block
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// // Must always return a BEGIN node, or nullptr - see GenFor construction
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generate_item
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~c~generate_item
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{ $$ = $1 ? (new AstBegin{$1->fileline(), "", $1, true, true}) : nullptr; }
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| genItemBegin { $$ = $1; }
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| ~c~genItemBegin { $$ = $1; }
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;
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c_generate_block_or_null<nodep>: // IEEE: generate_block_or_null (for checkers)
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BISONPRE_COPY(generate_block_or_null,{s/~c~/c_/g}) // {copied}
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;
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genItemBegin<nodep>: // IEEE: part of generate_block
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@ -2725,27 +2731,27 @@ genItemBegin<nodep>: // IEEE: part of generate_block
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{ $$ = nullptr; GRAMMARP->endLabel($<fl>5, *$3, $5); }
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;
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//UNSUPc_genItemBegin<nodep>: // IEEE: part of generate_block (for checkers)
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//UNSUP BISONPRE_COPY(genItemBegin,{s/~c~/c_/g}) // {copied}
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//UNSUP ;
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c_genItemBegin<nodep>: // IEEE: part of generate_block (for checkers)
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BISONPRE_COPY(genItemBegin,{s/~c~/c_/g}) // {copied}
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;
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genItemOrBegin<nodep>: // Not in IEEE, but our begin isn't under generate_item
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~c~generate_item { $$ = $1; }
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| ~c~genItemBegin { $$ = $1; }
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;
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//UNSUPc_genItemOrBegin<nodep>: // (for checkers)
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//UNSUP BISONPRE_COPY(genItemOrBegin,{s/~c~/c_/g}) // {copied}
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//UNSUP ;
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c_genItemOrBegin<nodep>: // (for checkers)
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BISONPRE_COPY(genItemOrBegin,{s/~c~/c_/g}) // {copied}
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;
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genItemList<nodep>:
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~c~genItemOrBegin { $$ = $1; }
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| ~c~genItemList ~c~genItemOrBegin { $$ = addNextNull($1, $2); }
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;
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//UNSUPc_genItemList<nodep>: // (for checkers)
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//UNSUP BISONPRE_COPY(genItemList,{s/~c~/c_/g}) // {copied}
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//UNSUP ;
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c_genItemList<nodep>: // (for checkers)
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BISONPRE_COPY(genItemList,{s/~c~/c_/g}) // {copied}
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;
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generate_item<nodep>: // IEEE: module_or_interface_or_generate_item
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// // Only legal when in a generate under a module (or interface under a module)
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@ -2757,9 +2763,9 @@ generate_item<nodep>: // IEEE: module_or_interface_or_generate_item
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// // so below in c_generate_item
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;
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//UNSUPc_generate_item<nodep>: // IEEE: generate_item (for checkers)
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//UNSUP checker_or_generate_item { $$ = $1; }
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//UNSUP ;
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c_generate_item<nodep>: // IEEE: generate_item (for checkers)
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checker_or_generate_item { $$ = $1; }
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;
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conditional_generate_construct<nodep>: // ==IEEE: conditional_generate_construct
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yCASE '(' expr ')' ~c~case_generate_itemListE yENDCASE
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@ -2770,9 +2776,9 @@ conditional_generate_construct<nodep>: // ==IEEE: conditional_generate_construc
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{ $$ = new AstGenIf{$1, $3, $5, $7}; }
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;
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//UNSUPc_conditional_generate_construct<nodep>: // IEEE: conditional_generate_construct (for checkers)
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//UNSUP BISONPRE_COPY(conditional_generate_construct,{s/~c~/c_/g}) // {copied}
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//UNSUP ;
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c_conditional_generate_construct<nodep>: // IEEE: conditional_generate_construct (for checkers)
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BISONPRE_COPY(conditional_generate_construct,{s/~c~/c_/g}) // {copied}
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;
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loop_generate_construct<nodep>: // ==IEEE: loop_generate_construct
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yFOR '(' genvar_initialization ';' expr ';' genvar_iteration ')' ~c~generate_block_or_null
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@ -2801,9 +2807,9 @@ loop_generate_construct<nodep>: // ==IEEE: loop_generate_construct
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}
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;
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//UNSUPc_loop_generate_construct<nodep>: // IEEE: loop_generate_construct (for checkers)
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//UNSUP BISONPRE_COPY(loop_generate_construct,{s/~c~/c_/g}) // {copied}
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//UNSUP ;
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c_loop_generate_construct<nodep>: // IEEE: loop_generate_construct (for checkers)
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BISONPRE_COPY(loop_generate_construct,{s/~c~/c_/g}) // {copied}
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;
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genvar_initialization<nodep>: // ==IEEE: genvar_initialization
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varRefBase '=' expr { $$ = new AstAssign{$2, $1, $3}; }
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@ -2855,7 +2861,11 @@ genvar_iteration<nodep>: // ==IEEE: genvar_iteration
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case_generate_itemListE<caseItemp>: // IEEE: [{ case_generate_itemList }]
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/* empty */ { $$ = nullptr; }
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| case_generate_itemList { $$ = $1; }
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| ~c~case_generate_itemList { $$ = $1; }
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;
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c_case_generate_itemListE<caseItemp>: // IEEE: { case_generate_item } (for checkers)
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BISONPRE_COPY(case_generate_itemListE,{s/~c~/c_/g}) // {copied}
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;
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case_generate_itemList<caseItemp>: // IEEE: { case_generate_itemList }
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@ -2863,19 +2873,19 @@ case_generate_itemList<caseItemp>: // IEEE: { case_generate_itemList }
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| ~c~case_generate_itemList ~c~case_generate_item { $$ = $1; $1->addNext($2); }
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;
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//UNSUPc_case_generate_itemList<nodep>: // IEEE: { case_generate_item } (for checkers)
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//UNSUP BISONPRE_COPY(case_generate_itemList,{s/~c~/c_/g}) // {copied}
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//UNSUP ;
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case_generate_item<caseItemp>: // ==IEEE: case_generate_item
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caseCondList colon generate_block_or_null { $$ = new AstCaseItem{$2, $1, $3}; }
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| yDEFAULT colon generate_block_or_null { $$ = new AstCaseItem{$1, nullptr, $3}; }
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| yDEFAULT generate_block_or_null { $$ = new AstCaseItem{$1, nullptr, $2}; }
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c_case_generate_itemList<caseItemp>: // IEEE: { case_generate_item } (for checkers)
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BISONPRE_COPY(case_generate_itemList,{s/~c~/c_/g}) // {copied}
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;
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//UNSUPc_case_generate_item<nodep>: // IEEE: case_generate_item (for checkers)
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//UNSUP BISONPRE_COPY(case_generate_item,{s/~c~/c_/g}) // {copied}
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//UNSUP ;
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case_generate_item<caseItemp>: // ==IEEE: case_generate_item
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caseCondList colon ~c~generate_block_or_null { $$ = new AstCaseItem{$2, $1, $3}; }
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| yDEFAULT colon ~c~generate_block_or_null { $$ = new AstCaseItem{$1, nullptr, $3}; }
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| yDEFAULT ~c~generate_block_or_null { $$ = new AstCaseItem{$1, nullptr, $2}; }
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;
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c_case_generate_item<caseItemp>: // IEEE: case_generate_item (for checkers)
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BISONPRE_COPY(case_generate_item,{s/~c~/c_/g}) // {copied}
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;
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//************************************************
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// Assignments and register declarations
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@ -5935,7 +5945,6 @@ pexpr<nodeExprp>: // IEEE: property_expr (The name pexpr is important as regex
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complex_pexpr<nodeExprp>: // IEEE: part of property_expr, see comments there
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expr yP_ORMINUSGT pexpr { $$ = new AstLogOr{$2, new AstLogNot{$2, $1}, $3}; }
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| expr yP_OREQGT pexpr { $$ = new AstImplication{$2, $1, $3}; }
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| yNOT pexpr %prec prNEGATION { $$ = new AstLogNot{$1, $2}; }
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| '(' complex_pexpr ')' { $$ = $2; }
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//UNSUP remove above, use below:
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//
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@ -5945,7 +5954,7 @@ complex_pexpr<nodeExprp>: // IEEE: part of property_expr, see comments there
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// // IEEE: '(' pexpr ')'
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// // Expanded below
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//
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//UNSUP yNOT pexpr %prec prNEGATION { }
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| yNOT pexpr %prec prNEGATION { $$ = new AstLogNot{$1, $2}; }
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//UNSUP ySTRONG '(' sexpr ')' { }
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//UNSUP yWEAK '(' sexpr ')' { }
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// // IEEE: pexpr yOR pexpr
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@ -6249,7 +6258,8 @@ complex_pexpr<nodeExprp>: // IEEE: part of property_expr, see comments there
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//UNSUPlist_of_cross_items<nodep>: // ==IEEE: list_of_cross_items
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//UNSUP cross_item ',' cross_item { $$ = addNextNull($1, $3); }
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//UNSUP | cross_item ',' cross_item ',' cross_itemList { }
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//UNSUP | cross_item ',' cross_item ',' cross_itemList
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//UNSUP { $$ = addNextNull(addNextNull($1, $3), $5); }
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//UNSUP ;
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//UNSUPcross_itemList<nodep>: // IEEE: part of list_of_cross_items
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@ -6459,67 +6469,85 @@ rs_case_item<nodep>: // ==IEEE: rs_case_item
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//**********************************************************************
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// Checker
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//UNSUPchecker_declaration<nodep>: // ==IEEE: part of checker_declaration
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//UNSUP checkerFront checker_port_listE ';'
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//UNSUP checker_or_generate_itemListE yENDCHECKER endLabelE
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//UNSUP { SYMP->popScope($$); }
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//UNSUP ;
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checker_declaration<nodep>: // ==IEEE: part of checker_declaration
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checkerFront checker_port_listE ';'
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checker_or_generate_itemListE yENDCHECKER endLabelE
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{ $$ = $1;
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$1->modTrace(GRAMMARP->allTracingOn($1->fileline()));
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if ($2) $1->addStmtsp($2);
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if ($4) $1->addStmtsp($4);
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GRAMMARP->m_modp = nullptr;
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SYMP->popScope($1);
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GRAMMARP->endLabel($<fl>6, $1, $6); }
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;
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//UNSUPcheckerFront<nodep>: // IEEE: part of checker_declaration
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//UNSUP yCHECKER idAny/*checker_identifier*/
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//UNSUP { SYMP->pushNew($$); }
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//UNSUP ;
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checkerFront<nodeModulep>: // IEEE: part of checker_declaration
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yCHECKER idAny/*checker_identifier*/
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{ BBUNSUP($<fl>1, "Unsupported: checker");
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// TODO should be AstChecker not AstModule
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$$ = new AstModule{$<fl>2, *$2};
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$$->modTrace(GRAMMARP->allTracingOn($$->fileline()));
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$$->timeunit(PARSEP->timeLastUnit());
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$$->unconnectedDrive(PARSEP->unconnectedDrive());
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SYMP->pushNew($$);
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GRAMMARP->m_modp = $$; }
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;
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//UNSUPchecker_port_listE<nodep>: // IEEE: [ ( [ checker_port_list ] ) ]
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//UNSUP // // checker_port_item is basically the same as property_port_item, minus yLOCAL::
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//UNSUP // // Want to bet 1800-2012 adds local to checkers?
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//UNSUP property_port_listE { $$ = $1; }
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//UNSUP ;
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checker_port_listE<nodep>: // IEEE: [ ( [ checker_port_list ] ) ]
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// // checker_port_item is basically the same as property_port_item, minus yLOCAL::
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// // Want to bet 1800-2012 adds local to checkers?
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property_port_listE { $$ = $1; }
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;
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//UNSUPchecker_or_generate_itemListE<nodep>: // IEEE: [{ checker_or_generate_itemList }]
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//UNSUP /* empty */ { $$ = nullptr; }
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//UNSUP | checker_or_generate_itemList { $$ = $1; }
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//UNSUP ;
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checker_or_generate_itemListE<nodep>: // IEEE: [{ checker_or_generate_itemList }]
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/* empty */ { $$ = nullptr; }
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| checker_or_generate_itemList { $$ = $1; }
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;
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//UNSUPchecker_or_generate_itemList<nodep>: // IEEE: { checker_or_generate_itemList }
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//UNSUP checker_or_generate_item { $$ = $1; }
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//UNSUP | checker_or_generate_itemList checker_or_generate_item { $$ = addNextNull($1, $2); }
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//UNSUP ;
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checker_or_generate_itemList<nodep>: // IEEE: { checker_or_generate_itemList }
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checker_or_generate_item { $$ = $1; }
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| checker_or_generate_itemList checker_or_generate_item { $$ = addNextNull($1, $2); }
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;
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//UNSUPchecker_or_generate_item<nodep>: // ==IEEE: checker_or_generate_item
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//UNSUP checker_or_generate_item_declaration { $$ = $1; }
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//UNSUP | initial_construct { $$ = $1; }
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//UNSUP // // IEEE: checker_construct
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//UNSUP | yALWAYS stmtBlock { }
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//UNSUP | final_construct { $$ = $1; }
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//UNSUP | assertion_item { $$ = $1; }
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//UNSUP | continuous_assign { $$ = $1; }
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//UNSUP | checker_generate_item { $$ = $1; }
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//UNSUP ;
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checker_or_generate_item<nodep>: // ==IEEE: checker_or_generate_item
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checker_or_generate_item_declaration { $$ = $1; }
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| initial_construct { $$ = $1; }
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// // IEEE: checker_construct
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| always_construct { $$ = $1; }
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| final_construct { $$ = $1; }
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| assertion_item { $$ = $1; }
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| continuous_assign { $$ = $1; }
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| checker_generate_item { $$ = $1; }
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;
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//UNSUPchecker_or_generate_item_declaration<nodep>: // ==IEEE: checker_or_generate_item_declaration
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//UNSUP data_declaration { $$ = $1; }
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//UNSUP | yRAND data_declaration { }
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//UNSUP | function_declaration { $$ = $1; }
|
||||
//UNSUP | checker_declaration { $$ = $1; }
|
||||
//UNSUP | assertion_item_declaration { $$ = $1; }
|
||||
//UNSUP | covergroup_declaration { $$ = $1; }
|
||||
//UNSUP // // IEEE deprecated: overload_declaration
|
||||
//UNSUP | genvar_declaration { $$ = $1; }
|
||||
//UNSUP | clocking_declaration { $$ = $1; }
|
||||
//UNSUP | yDEFAULT yCLOCKING id/*clocking_identifier*/ ';' { }
|
||||
//UNSUP | yDEFAULT yDISABLE yIFF expr/*expression_or_dist*/ ';' { }
|
||||
//UNSUP | ';' { $$ = nullptr; }
|
||||
//UNSUP ;
|
||||
checker_or_generate_item_declaration<nodep>: // ==IEEE: checker_or_generate_item_declaration
|
||||
data_declaration
|
||||
{ $$ = $1; BBUNSUP($1, "Unsupported: checker data declaration"); }
|
||||
| yRAND data_declaration
|
||||
{ $$ = $2; BBUNSUP($1, "Unsupported: checker rand"); }
|
||||
| function_declaration { $$ = $1; }
|
||||
| checker_declaration
|
||||
{ $$ = nullptr; BBUNSUP($1, "Unsupported: recursive checker"); }
|
||||
| assertion_item_declaration { $$ = $1; }
|
||||
//UNSUP covergroup_declaration { $$ = $1; }
|
||||
// // IEEE deprecated: overload_declaration
|
||||
| genvar_declaration { $$ = $1; }
|
||||
| clocking_declaration { $$ = $1; }
|
||||
| yDEFAULT yCLOCKING id/*clocking_identifier*/ ';' { }
|
||||
{ $$ = nullptr; BBUNSUP($1, "Unsupported: checker default clocking"); }
|
||||
| yDEFAULT yDISABLE yIFF expr/*expression_or_dist*/ ';' { }
|
||||
{ $$ = nullptr; BBUNSUP($1, "Unsupported: checker default disable iff"); }
|
||||
| ';' { $$ = nullptr; }
|
||||
;
|
||||
|
||||
//UNSUPchecker_generate_item<nodep>: // ==IEEE: checker_generate_item
|
||||
//UNSUP // // Specialized for checker so need "c_" prefixes here
|
||||
//UNSUP c_loop_generate_construct { $$ = $1; }
|
||||
//UNSUP | c_conditional_generate_construct { $$ = $1; }
|
||||
//UNSUP | c_generate_region { $$ = $1; }
|
||||
//UNSUP //
|
||||
//UNSUP | elaboration_system_task { $$ = $1; }
|
||||
//UNSUP ;
|
||||
checker_generate_item<nodep>: // ==IEEE: checker_generate_item
|
||||
// // Specialized for checker so need "c_" prefixes here
|
||||
c_loop_generate_construct { $$ = $1; }
|
||||
| c_conditional_generate_construct { $$ = $1; }
|
||||
| c_generate_region { $$ = $1; }
|
||||
//
|
||||
| elaboration_system_task { $$ = $1; }
|
||||
;
|
||||
|
||||
//UNSUPchecker_instantiation<nodep>:
|
||||
//UNSUP // // Only used for procedural_assertion_item's
|
||||
|
||||
38
test_regress/t/t_checker.out
Normal file
38
test_regress/t/t_checker.out
Normal file
@ -0,0 +1,38 @@
|
||||
%Error-UNSUPPORTED: t/t_checker.v:33:1: Unsupported: checker
|
||||
33 | checker Chk
|
||||
| ^~~~~~~
|
||||
... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest
|
||||
%Error-UNSUPPORTED: t/t_checker.v:36:8: Unsupported: checker data declaration
|
||||
36 | bit clk;
|
||||
| ^~~
|
||||
%Error-UNSUPPORTED: t/t_checker.v:37:8: Unsupported: checker data declaration
|
||||
37 | bit in;
|
||||
| ^~
|
||||
%Error-UNSUPPORTED: t/t_checker.v:38:8: Unsupported: checker data declaration
|
||||
38 | bit rst;
|
||||
| ^~~
|
||||
%Error-UNSUPPORTED: t/t_checker.v:39:4: Unsupported: checker rand
|
||||
39 | rand bit randed;
|
||||
| ^~~~
|
||||
%Error-UNSUPPORTED: t/t_checker.v:41:8: Unsupported: checker data declaration
|
||||
41 | int counter = 0;
|
||||
| ^~~~~~~
|
||||
%Error-UNSUPPORTED: t/t_checker.v:43:8: Unsupported: checker data declaration
|
||||
43 | int ival;
|
||||
| ^~~~
|
||||
%Error-UNSUPPORTED: t/t_checker.v:53:8: Unsupported: checker data declaration
|
||||
53 | int ival2;
|
||||
| ^~~~~
|
||||
%Error-UNSUPPORTED: t/t_checker.v:61:4: Unsupported: checker default clocking
|
||||
61 | default clocking clk;
|
||||
| ^~~~~~~
|
||||
%Error-UNSUPPORTED: t/t_checker.v:62:4: Unsupported: checker default disable iff
|
||||
62 | default disable iff rst;
|
||||
| ^~~~~~~
|
||||
%Error-UNSUPPORTED: t/t_checker.v:64:4: Unsupported: checker
|
||||
64 | checker ChkChk;
|
||||
| ^~~~~~~
|
||||
%Error-UNSUPPORTED: t/t_checker.v:64:12: Unsupported: recursive checker
|
||||
64 | checker ChkChk;
|
||||
| ^~~~~~
|
||||
%Error: Exiting due to
|
||||
24
test_regress/t/t_checker.pl
Executable file
24
test_regress/t/t_checker.pl
Executable file
@ -0,0 +1,24 @@
|
||||
#!/usr/bin/env perl
|
||||
if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
|
||||
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
|
||||
#
|
||||
# Copyright 2023 by Wilson Snyder. This program is free software; you
|
||||
# can redistribute it and/or modify it under the terms of either the GNU
|
||||
# Lesser General Public License Version 3 or the Perl Artistic License
|
||||
# Version 2.0.
|
||||
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
|
||||
|
||||
scenarios(vlt => 1);
|
||||
|
||||
compile(
|
||||
verilator_flags2 => ['--assert'],
|
||||
expect_filename => $Self->{golden_filename},
|
||||
fails => 1,
|
||||
);
|
||||
|
||||
#execute(
|
||||
# check_finished => 1,
|
||||
# );
|
||||
|
||||
ok(1);
|
||||
1;
|
||||
80
test_regress/t/t_checker.v
Normal file
80
test_regress/t/t_checker.v
Normal file
@ -0,0 +1,80 @@
|
||||
// DESCRIPTION: Verilator: Verilog Test module
|
||||
//
|
||||
// This file ONLY is placed under the Creative Commons Public Domain, for
|
||||
// any use, without warranty, 2023 by Wilson Snyder.
|
||||
// SPDX-License-Identifier: CC0-1.0
|
||||
|
||||
module t(/*AUTOARG*/
|
||||
// Inputs
|
||||
clk
|
||||
);
|
||||
input clk;
|
||||
|
||||
integer cyc = 0;
|
||||
|
||||
// Test loop
|
||||
always @ (posedge clk) begin
|
||||
`ifdef TEST_VERBOSE
|
||||
$write("[%0t] cyc==%0d\n", $time, cyc);
|
||||
`endif
|
||||
cyc <= cyc + 1;
|
||||
if (cyc == 0) begin
|
||||
end
|
||||
else if (cyc == 99) begin
|
||||
$write("*-* All Finished *-*\n");
|
||||
$finish;
|
||||
end
|
||||
end
|
||||
|
||||
Chk check(clk, cyc);
|
||||
|
||||
endmodule
|
||||
|
||||
checker Chk
|
||||
// UNSUP (input clk, int in)
|
||||
;
|
||||
bit clk;
|
||||
bit in;
|
||||
bit rst;
|
||||
rand bit randed; // TODO test this
|
||||
|
||||
int counter = 0;
|
||||
|
||||
int ival;
|
||||
final if (ival != 1234) $stop;
|
||||
genvar g;
|
||||
if (0) begin
|
||||
initial ival = 1;
|
||||
end
|
||||
else begin
|
||||
initial ival = 1234;
|
||||
end
|
||||
|
||||
int ival2;
|
||||
case (1)
|
||||
0: initial ival2 = 0;
|
||||
default: initial ival2 = 12345;
|
||||
endcase
|
||||
final if (ival2 != 12345) $stop;
|
||||
|
||||
|
||||
default clocking clk; // TODO test this
|
||||
default disable iff rst; // TODO test this
|
||||
|
||||
checker ChkChk; // TODO flag unsupported
|
||||
endchecker
|
||||
|
||||
function automatic int f; // TODO test this
|
||||
endfunction
|
||||
|
||||
|
||||
clocking cb1 @(posedge clk); // TODO test this
|
||||
input in;
|
||||
output out;
|
||||
endclocking
|
||||
|
||||
always_ff @(posedge clk)
|
||||
counter <= counter + 1'b1;
|
||||
|
||||
a1: assert property (@(posedge clk) counter == in);
|
||||
endchecker
|
||||
Loading…
Reference in New Issue
Block a user