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Commentary, fix copyright

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Wilson Snyder 2023-02-28 01:09:09 -05:00
parent a0997d0b98
commit d9a0e69597
1 changed files with 1 additions and 1 deletions
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test_regress/t/t_timing_wait_long.pl
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@ -2,7 +2,7 @@
if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2022 by Antmicro Ltd. This program is free software; you
# Copyright 2022 by Wilson Snyder. This program is free software; you
# can redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.