diff --git a/test_regress/t/t_interface_parent_scope_bad.pl b/test_regress/t/t_interface_parent_scope_bad.pl
new file mode 100755
index 000000000..89a1fffda
--- /dev/null
+++ b/test_regress/t/t_interface_parent_scope_bad.pl
@@ -0,0 +1,20 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2019 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+
+$Self->{vlt_all} and unsupported("Verilator unsupported, bug1623");
+
+scenarios(linter => 1);
+
+lint(
+    fails => 1,
+    expect_filename => $Self->{golden_filename},
+    );
+
+ok(1);
+1;
diff --git a/test_regress/t/t_interface_parent_scope_bad.v b/test_regress/t/t_interface_parent_scope_bad.v
new file mode 100644
index 000000000..a8070445a
--- /dev/null
+++ b/test_regress/t/t_interface_parent_scope_bad.v
@@ -0,0 +1,32 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2019 by Driss Hafdi
+
+interface Foo();
+   logic quux;
+endinterface
+
+module Bar();
+   always_comb foo.quux = '0;
+endmodule
+
+module Baz();
+   Foo foo();
+   Bar bar();
+endmodule
+
+module t (/*AUTOARG*/
+   // Inputs
+   clk
+   );
+
+   input clk;
+
+   Baz baz();
+
+   initial begin
+      $write("*-* All Finished *-*\n");
+      $finish;
+   end
+endmodule