Fix huge shifts to zero with -Wno-WIDTH, bug765.

Changes

@@ -5,6 +5,8 @@ indicates the contributor was also the author of the fix; Thanks!
 
 * Verilator 3.861 devel
 
+****  Fix huge shifts to zero with -Wno-WIDTH, bug765. [Clifford Wolf]
+
 
 * Verilator 3.860 2014-05-11
 

include/verilated.h

@@ -1458,7 +1458,7 @@ static inline QData VL_STREAML_QQI(int, int lbits, int, QData ld, IData rd) {
 static inline WDataOutP VL_STREAML_WWI(int, int lbits, int, WDataOutP owp, WDataInP lwp, IData rd) {
     VL_ZERO_RESET_W(lbits, owp);
     // Slice size should never exceed the lhs width
-    int ssize = ((int)rd < lbits) ? ((int)rd) : lbits;
+    int ssize = (rd < (IData)lbits) ? rd : ((IData)lbits);
     for (int istart=0; istart<lbits; istart+=rd) {
 	int ostart=lbits-rd-istart;
         ostart = ostart > 0 ? ostart : 0;
@@ -1558,7 +1558,7 @@ static inline void _VL_SHIFTL_INPLACE_W(int obits,WDataOutP iowp,IData rd/*1 or
 static inline WDataOutP VL_SHIFTL_WWI(int obits,int,int,WDataOutP owp,WDataInP lwp, IData rd) {
     int word_shift = VL_BITWORD_I(rd);
     int bit_shift = VL_BITBIT_I(rd);
-    if ((int)rd >= obits) {
+    if (rd >= (IData)obits) {  // rd may be huge with MSB set
 	for (int i=0; i < VL_WORDS_I(obits); i++) owp[i] = 0;
     } else if (bit_shift==0) {  // Aligned word shift (<<0,<<32,<<64 etc)
 	for (int i=0; i < word_shift; i++) owp[i] = 0;
@@ -1576,7 +1576,7 @@ static inline WDataOutP VL_SHIFTL_WWI(int obits,int,int,WDataOutP owp,WDataInP l
 static inline WDataOutP VL_SHIFTR_WWI(int obits,int,int,WDataOutP owp,WDataInP lwp, IData rd) {
     int word_shift = VL_BITWORD_I(rd);  // Maybe 0
     int bit_shift = VL_BITBIT_I(rd);
-    if ((int)rd >= obits) {
+    if (rd >= (IData)obits) {  // rd may be huge with MSB set
 	for (int i=0; i < VL_WORDS_I(obits); i++) owp[i] = 0;
     } else if (bit_shift==0) {  // Aligned word shift (>>0,>>32,>>64 etc)
 	int copy_words = (VL_WORDS_I(obits)-word_shift);
@@ -1622,7 +1622,7 @@ static inline WDataOutP VL_SHIFTRS_WWI(int obits,int lbits,int,WDataOutP owp,WDa
     int bit_shift = VL_BITBIT_I(rd);
     int lmsw = VL_WORDS_I(obits)-1;
     IData sign = VL_SIGNONES_I(lbits,lwp[lmsw]);
-    if ((int)rd >= obits) {  // Shifting past end, sign in all of lbits
+    if (rd >= (IData)obits) {  // Shifting past end, sign in all of lbits
 	for (int i=0; i <= lmsw; i++) owp[i] = sign;
 	owp[lmsw] &= VL_MASK_I(lbits);
     } else if (bit_shift==0) {  // Aligned word shift (>>0,>>32,>>64 etc)
@@ -1661,7 +1661,7 @@ static inline WDataOutP VL_SHIFTRS_WWI(int obits,int lbits,int,WDataOutP owp,WDa
 
 static inline IData VL_BITSEL_IWII(int, int lbits, int, int, WDataInP lwp, IData rd) {
     int word = VL_BITWORD_I(rd);
-    if (VL_UNLIKELY((int)rd>lbits)) {
+    if (VL_UNLIKELY(rd>(IData)lbits)) {
 	return ~0; // Spec says you can go outside the range of a array.  Don't coredump if so.
 	// We return all 1's as that's more likely to find bugs (?) than 0's.
     } else {

src/V3Number.cpp

@@ -103,7 +103,7 @@ V3Number::V3Number (FileLine* fileline, const char* sourcep) {
     }
     // Otherwise...
     else if (!m_sized) {
-	width(32, false); // Says the spec.
+	width(32, false); // Says IEEE 1800-2012 5.7.1
 	if (unbased) isSigned(true); // Also says the spec.
     }
 

test_regress/t/t_math_shift_rep.pl

@@ -0,0 +1,19 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+
+compile (
+    verilator_flags2 => ["-CFLAGS '-DVL_DEBUG -ggdb -O0'"],
+    );
+
+execute (
+    check_finished=>1,
+    );
+
+ok(1);
+1;

test_regress/t/t_math_shift_rep.v

@@ -0,0 +1,77 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2014 by Wilson Snyder.
+
+module t (/*AUTOARG*/
+   // Inputs
+   clk
+   );
+
+   input clk;
+
+   integer 	cyc=0;
+   reg [63:0] 	crc;
+   reg [63:0] 	sum;
+
+   //bug765; disappears if add this wire
+   //wire [7:0]  a = (crc[7] ? {7'b0,crc[0]} : crc[7:0]);  // favor low values
+   wire [7:0]  a = crc[7:0];
+
+   /*AUTOWIRE*/
+   // Beginning of automatic wires (for undeclared instantiated-module outputs)
+   wire [15:0]		y;			// From test of Test.v
+   // End of automatics
+
+   Test test (/*AUTOINST*/
+	      // Outputs
+	      .y			(y[15:0]),
+	      // Inputs
+	      .a			(a[7:0]));
+
+   // Aggregate outputs into a single result vector
+   wire [63:0] result = {48'h0, y};
+
+   // Test loop
+   always @ (posedge clk) begin
+`ifdef TEST_VERBOSE
+      $write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
+`endif
+      cyc <= cyc + 1;
+      crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
+      sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
+      if (cyc==0) begin
+	 // Setup
+	 crc <= 64'h5aef0c8d_d70a4497;
+	 sum <= 64'h0;
+      end
+      else if (cyc<10) begin
+	 sum <= 64'h0;
+      end
+      else if (cyc<90) begin
+      end
+      else if (cyc==99) begin
+	 $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
+	 if (crc !== 64'hc77bb9b3784ea091) $stop;
+	 // What checksum will we end up with (above print should match)
+`define EXPECTED_SUM 64'h0
+	 if (sum !== `EXPECTED_SUM) $stop;
+	 $write("*-* All Finished *-*\n");
+	 $finish;
+      end
+   end
+
+endmodule
+
+module Test (/*AUTOARG*/
+   // Outputs
+   y,
+   // Inputs
+   a
+   );
+   input signed [7:0] a;
+   output [15:0]      y;
+   // verilator lint_off WIDTH
+   assign y = ~66'd0 <<< {4{a}};
+   // verilator lint_on WIDTH
+endmodule