From ae8d8ee1ac85c248105f9fda00a7f7d1a73a91e1 Mon Sep 17 00:00:00 2001
From: Wilson Snyder <wsnyder@wsnyder.org>
Date: Sun, 15 May 2022 09:29:15 -0400
Subject: [PATCH 01/23] Fix crash with misuse of display.

---
 src/V3EmitCFunc.cpp     |  3 ++-
 test_regress/t/t_with.v | 36 ++++++++++++++++++++++++------------
 2 files changed, 26 insertions(+), 13 deletions(-)

diff --git a/src/V3EmitCFunc.cpp b/src/V3EmitCFunc.cpp
index 786b8368c..2aa4f2342 100644
--- a/src/V3EmitCFunc.cpp
+++ b/src/V3EmitCFunc.cpp
@@ -308,7 +308,8 @@ void EmitCFunc::displayArg(AstNode* dispp, AstNode** elistp, bool isScan, const
     }
     emitDispState.pushFormat(pfmt);
     if (!ignore) {
-        if (argp->dtypep()->basicp()->keyword() == VBasicDTypeKwd::STRING) {
+        if (argp->dtypep()->basicp()
+            && argp->dtypep()->basicp()->keyword() == VBasicDTypeKwd::STRING) {
             // string in SystemVerilog is std::string in C++ which is not POD
             emitDispState.pushArg(' ', nullptr, "-1");
         } else {
diff --git a/test_regress/t/t_with.v b/test_regress/t/t_with.v
index 3a3da8ff2..64684e46c 100644
--- a/test_regress/t/t_with.v
+++ b/test_regress/t/t_with.v
@@ -6,40 +6,52 @@
 // any use, without warranty, 2020 by Wilson Snyder.
 // SPDX-License-Identifier: CC0-1.0
 
+`define stop $stop
+`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d:  got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
+
 module t (/*AUTOARG*/);
 
    initial begin
       int tofind;
       int aliases[$];
       int found[$];
-      int id;
       int i;
 
       aliases = '{ 1, 4, 6, 8};
       tofind = 6;
       found = aliases.find with (item == 1);
+      `checkh(found.size, 1);
       found = aliases.find(j) with (j == tofind);
+      `checkh(found.size, 1);
       // And as function
       aliases.find(i) with (i == tofind);
 
       // No parenthesis
-      found = aliases.find with (item == i);
-      aliases.find with (item == i);
+      tofind = 0;
+      found = aliases.find with (item == tofind);
+      `checkh(found.size, 0);
+      aliases.find with (item == tofind);
 
-`ifdef VERILATOR
-      // No expression (e.g. x.randomize() with {})
-      // Hack until randomize() supported
-      found = aliases.sort() with {};
-`endif
+      // bug3387
+      i = aliases.sum();
+      `checkh(i, 'h13);
+      i = aliases.sum() with (2'(item));
+      `checkh(i, 'h3);
 
       // Unique (array method)
-      id = 4;
-      found = aliases.find with (id);
-      found = aliases.find() with (item == id);
-      found = aliases.find(i) with (i == id);
+      tofind = 4;
+      found = aliases.find with (tofind);  // "true" match
+      `checkh(found.size, 4);
+      found = aliases.find() with (item == tofind);
+      `checkh(found.size, 1);
+      found = aliases.find(i) with (i == tofind);
+      `checkh(found.size, 1);
       i = aliases.or(v) with (v);
+      `checkh(i, 'hf);
       i = aliases.and(v) with (v);
+      `checkh(i, 0);
       i = aliases.xor(v) with (v);
+      `checkh(i, 'hb);
 
       $write("*-* All Finished *-*\n");
       $finish;

From 3c4131d45dc2be40e21494ca44664abd0ab14071 Mon Sep 17 00:00:00 2001
From: Wilson Snyder <wsnyder@wsnyder.org>
Date: Sun, 15 May 2022 09:53:48 -0400
Subject: [PATCH 02/23] Fix 'with' operator with type casting (#3387).

---
 Changes                 | 1 +
 src/V3LinkDot.cpp       | 1 -
 src/V3Width.cpp         | 4 ++--
 test_regress/t/t_with.v | 5 +++--
 4 files changed, 6 insertions(+), 5 deletions(-)

diff --git a/Changes b/Changes
index c3958d189..85b3f62bb 100644
--- a/Changes
+++ b/Changes
@@ -15,6 +15,7 @@ Verilator 4.223 devel
 
 * Support compile time trace signal selection with tracing_on/off (#3323). [Shunyao CAD]
 * Fix hang with large case statement optimization (#3405). [Mike Urbach]
+* Fix 'with' operator with type casting (#3387). [xiak95]
 
 
 Verilator 4.222 2022-05-02
diff --git a/src/V3LinkDot.cpp b/src/V3LinkDot.cpp
index 535f57b40..22f4d97ca 100644
--- a/src/V3LinkDot.cpp
+++ b/src/V3LinkDot.cpp
@@ -1729,7 +1729,6 @@ class LinkDotScopeVisitor final : public VNVisitor {
     // Note we allow AstNodeStmt's as generates may be under them
     virtual void visit(AstCell*) override {}
     virtual void visit(AstVar*) override {}
-    virtual void visit(AstNodeMath*) override {}
     virtual void visit(AstNode* nodep) override { iterateChildren(nodep); }
 
 public:
diff --git a/src/V3Width.cpp b/src/V3Width.cpp
index 17e302ccc..f5e16ec21 100644
--- a/src/V3Width.cpp
+++ b/src/V3Width.cpp
@@ -2725,7 +2725,7 @@ private:
             methodCallLValueRecurse(nodep, nodep->fromp(), VAccess::READ);
             newp = new AstCMethodHard(nodep->fileline(), nodep->fromp()->unlinkFrBack(),
                                       "r_" + nodep->name(), withp);
-            newp->dtypeFrom(adtypep->subDTypep());
+            newp->dtypeFrom(withp ? withp->dtypep() : adtypep->subDTypep());
             if (!nodep->firstAbovep()) newp->makeStatement();
         } else if (nodep->name() == "min" || nodep->name() == "max" || nodep->name() == "unique"
                    || nodep->name() == "unique_index") {
@@ -2949,7 +2949,7 @@ private:
             methodCallLValueRecurse(nodep, nodep->fromp(), VAccess::READ);
             newp = new AstCMethodHard(nodep->fileline(), nodep->fromp()->unlinkFrBack(),
                                       "r_" + nodep->name(), withp);
-            newp->dtypeFrom(adtypep->subDTypep());
+            newp->dtypeFrom(withp ? withp->dtypep() : adtypep->subDTypep());
             if (!nodep->firstAbovep()) newp->makeStatement();
         } else if (nodep->name() == "reverse" || nodep->name() == "shuffle"
                    || nodep->name() == "sort" || nodep->name() == "rsort") {
diff --git a/test_regress/t/t_with.v b/test_regress/t/t_with.v
index 64684e46c..64f6485c5 100644
--- a/test_regress/t/t_with.v
+++ b/test_regress/t/t_with.v
@@ -16,6 +16,7 @@ module t (/*AUTOARG*/);
       int aliases[$];
       int found[$];
       int i;
+      byte byteq[$] = {2, -1, 127};
 
       aliases = '{ 1, 4, 6, 8};
       tofind = 6;
@@ -35,8 +36,8 @@ module t (/*AUTOARG*/);
       // bug3387
       i = aliases.sum();
       `checkh(i, 'h13);
-      i = aliases.sum() with (2'(item));
-      `checkh(i, 'h3);
+      i = byteq.sum() with (int'(item));
+      `checkh(i, 128);
 
       // Unique (array method)
       tofind = 4;

From 829437b20b2f37dd597b9dd2be927e79995c2073 Mon Sep 17 00:00:00 2001
From: Geza Lore <gezalore@gmail.com>
Date: Sun, 15 May 2022 15:25:46 +0100
Subject: [PATCH 03/23] Commentary - dependencies

---
 docs/guide/install.rst | 17 ++++++++++++-----
 1 file changed, 12 insertions(+), 5 deletions(-)

diff --git a/docs/guide/install.rst b/docs/guide/install.rst
index 753215d68..2c0a1134f 100644
--- a/docs/guide/install.rst
+++ b/docs/guide/install.rst
@@ -87,7 +87,7 @@ compiles under all the options above, plus using MSVC++.
 Install Prerequisites
 ---------------------
 
-To build or run Verilator you need these standard packages:
+To build or run Verilator, you need these standard packages:
 
 ::
 
@@ -98,13 +98,20 @@ To build or run Verilator you need these standard packages:
    sudo apt-get install libfl-dev  # Ubuntu only (ignore if gives error)
    sudo apt-get install zlibc zlib1g zlib1g-dev  # Ubuntu only (ignore if gives error)
 
-To build or run the following are optional but should be installed for good
-performance:
+To build or run Verilator, the following are optional but should be installed
+for good performance:
 
 ::
 
    sudo apt-get install ccache  # If present at build, needed for run
-   sudo apt-get install libgoogle-perftools-dev numactl perl-doc
+   sudo apt-get install libgoogle-perftools-dev numactl
+
+The following is optional but is recommended for nicely rendered command line
+help when running Verilator:
+
+::
+
+   sudo apt-get install perl-doc
 
 To build Verilator you will need to install these packages; these do not
 need to be present to run Verilator:
@@ -118,7 +125,7 @@ Those developing Verilator itself may also want these (see internals.rst):
 ::
 
    sudo apt-get install gdb graphviz cmake clang clang-format-11 gprof lcov
-   sudo pip3 install sphinx sphinx_rtd_theme breathe
+   sudo pip3 install sphinx sphinx_rtd_theme sphinxcontrib-spelling breathe
    cpan install Pod::Perldoc
    cpan install Parallel::Forker
 

From 5aa12e9b511e2fbd1338c7f242da313ad39355c9 Mon Sep 17 00:00:00 2001
From: Wilson Snyder <wsnyder@wsnyder.org>
Date: Sun, 15 May 2022 10:50:44 -0400
Subject: [PATCH 04/23] Add assert when VerilatedContext is mis-deleted
 (#3121).

---
 Changes                                      |  1 +
 docs/guide/connecting.rst                    |  3 +++
 examples/make_tracing_c/sim_main.cpp         |  2 ++
 include/verilated.cpp                        | 14 ++++++++++-
 include/verilated.h                          |  7 ++++++
 test_regress/driver.pl                       |  1 +
 test_regress/t/t_wrapper_del_context_bad.cpp | 22 +++++++++++++++++
 test_regress/t/t_wrapper_del_context_bad.out |  2 ++
 test_regress/t/t_wrapper_del_context_bad.pl  | 25 ++++++++++++++++++++
 test_regress/t/t_wrapper_del_context_bad.v   |  9 +++++++
 10 files changed, 85 insertions(+), 1 deletion(-)
 create mode 100644 test_regress/t/t_wrapper_del_context_bad.cpp
 create mode 100644 test_regress/t/t_wrapper_del_context_bad.out
 create mode 100755 test_regress/t/t_wrapper_del_context_bad.pl
 create mode 100644 test_regress/t/t_wrapper_del_context_bad.v

diff --git a/Changes b/Changes
index 85b3f62bb..615f7088f 100644
--- a/Changes
+++ b/Changes
@@ -14,6 +14,7 @@ Verilator 4.223 devel
 **Minor:**
 
 * Support compile time trace signal selection with tracing_on/off (#3323). [Shunyao CAD]
+* Add assert when VerilatedContext is mis-deleted (#3121). [Ruptert Swarbrick]
 * Fix hang with large case statement optimization (#3405). [Mike Urbach]
 * Fix 'with' operator with type casting (#3387). [xiak95]
 
diff --git a/docs/guide/connecting.rst b/docs/guide/connecting.rst
index 8259447b3..edfc3d67b 100644
--- a/docs/guide/connecting.rst
+++ b/docs/guide/connecting.rst
@@ -110,6 +110,9 @@ model.  Here is a simple example:
              Verilated::commandArgs(argc, argv);   // Remember args
 
              top = new Vtop;             // Create model
+             // Do not instead make Vtop as a file-scope static
+             // variable, as the "C++ static initialization order fiasco"
+             // may cause a crash
 
              top->reset_l = 0;           // Set some inputs
 
diff --git a/examples/make_tracing_c/sim_main.cpp b/examples/make_tracing_c/sim_main.cpp
index 04181850a..06d399901 100644
--- a/examples/make_tracing_c/sim_main.cpp
+++ b/examples/make_tracing_c/sim_main.cpp
@@ -34,6 +34,8 @@ int main(int argc, char** argv, char** env) {
     // Using unique_ptr is similar to
     // "VerilatedContext* contextp = new VerilatedContext" then deleting at end.
     const std::unique_ptr<VerilatedContext> contextp{new VerilatedContext};
+    // Do not instead make Vtop as a file-scope static variable, as the
+    // "C++ static initialization order fiasco" may cause a crash
 
     // Set debug level, 0 is off, 9 is highest presently used
     // May be overridden by commandArgs argument parsing
diff --git a/include/verilated.cpp b/include/verilated.cpp
index 782b8cf39..1f6fe3b4c 100644
--- a/include/verilated.cpp
+++ b/include/verilated.cpp
@@ -2289,7 +2289,17 @@ VerilatedContext::VerilatedContext()
 }
 
 // Must declare here not in interface, as otherwise forward declarations not known
-VerilatedContext::~VerilatedContext() {}
+VerilatedContext::~VerilatedContext() {
+    checkMagic(this);
+    m_magic = 0x1;  // Arbitrary but 0x1 is what Verilator src uses for a deleted pointer
+}
+
+void VerilatedContext::checkMagic(const VerilatedContext* contextp) {
+    if (VL_UNLIKELY(!contextp || contextp->m_magic != MAGIC)) {
+        VL_FATAL_MT("", 0, "",  // LCOV_EXCL_LINE
+                    "Attempt to create model using a bad/deleted VerilatedContext pointer");
+    }
+}
 
 VerilatedContext::Serialized::Serialized() {
     m_timeunit = VL_TIME_UNIT;  // Initial value until overriden by _Vconfigure
@@ -2657,6 +2667,7 @@ const VerilatedScopeNameMap* VerilatedContext::scopeNameMap() VL_MT_SAFE {
 
 VerilatedSyms::VerilatedSyms(VerilatedContext* contextp)
     : _vm_contextp__(contextp ? contextp : Verilated::threadContextp()) {
+    VerilatedContext::checkMagic(_vm_contextp__);
     Verilated::threadContextp(_vm_contextp__);
 #ifdef VL_THREADED
     __Vm_evalMsgQp = new VerilatedEvalMsgQueue;
@@ -2664,6 +2675,7 @@ VerilatedSyms::VerilatedSyms(VerilatedContext* contextp)
 }
 
 VerilatedSyms::~VerilatedSyms() {
+    VerilatedContext::checkMagic(_vm_contextp__);
 #ifdef VL_THREADED
     delete __Vm_evalMsgQp;
 #endif
diff --git a/include/verilated.h b/include/verilated.h
index 889f59c7b..aa1a582be 100644
--- a/include/verilated.h
+++ b/include/verilated.h
@@ -374,6 +374,10 @@ protected:
     // List of free descriptors in the MCT region [4, 32)
     std::vector<IData> m_fdFreeMct VL_GUARDED_BY(m_fdMutex);
 
+    // Magic to check for bad construction
+    static constexpr uint64_t MAGIC = 0xC35F9A6E5298EE6EULL;  // SHA256 "VerilatedContext"
+    uint64_t m_magic = MAGIC;
+
 private:
     // CONSTRUCTORS
     VL_UNCOPYABLE(VerilatedContext);
@@ -535,6 +539,9 @@ public:  // But for internal use only
     // Internal: Serialization setup
     static constexpr size_t serialized1Size() VL_PURE { return sizeof(m_s); }
     void* serialized1Ptr() VL_MT_UNSAFE { return &m_s; }
+
+    // Internal: Check magic number
+    static void checkMagic(const VerilatedContext* contextp);
 };
 
 //===========================================================================
diff --git a/test_regress/driver.pl b/test_regress/driver.pl
index 3f4db9538..ffcfac4a8 100755
--- a/test_regress/driver.pl
+++ b/test_regress/driver.pl
@@ -1892,6 +1892,7 @@ sub _make_main {
             $fh->print("        if (save_time && ${time} == save_time) {\n");
             $fh->print("            save_model(\"$self->{obj_dir}/saved.vltsv\");\n");
             $fh->print("            printf(\"Exiting after save_model\\n\");\n");
+            $fh->print("            topp.reset(nullptr);\n");
             $fh->print("            return 0;\n");
             $fh->print("        }\n");
         }
diff --git a/test_regress/t/t_wrapper_del_context_bad.cpp b/test_regress/t/t_wrapper_del_context_bad.cpp
new file mode 100644
index 000000000..e6e33decd
--- /dev/null
+++ b/test_regress/t/t_wrapper_del_context_bad.cpp
@@ -0,0 +1,22 @@
+//
+// DESCRIPTION: Verilator: Verilog Multiple Model Test Module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2022 by Wilson Snyder.
+// SPDX-License-Identifier: CC0-1.0
+
+#include <verilated.h>
+
+#include VM_PREFIX_INCLUDE
+
+int main(int argc, char** argv, char** env) {
+    // Create contexts
+    VerilatedContext* contextp{new VerilatedContext};
+
+    delete contextp;  // Test mistake - deleting contextp
+
+    // instantiate verilated design
+    std::unique_ptr<VM_PREFIX> topp{new VM_PREFIX{contextp, "TOP"}};
+
+    return 0;
+}
diff --git a/test_regress/t/t_wrapper_del_context_bad.out b/test_regress/t/t_wrapper_del_context_bad.out
new file mode 100644
index 000000000..6344c8d00
--- /dev/null
+++ b/test_regress/t/t_wrapper_del_context_bad.out
@@ -0,0 +1,2 @@
+%Error: Attempt to create model using a bad/deleted VerilatedContext pointer
+Aborting...
diff --git a/test_regress/t/t_wrapper_del_context_bad.pl b/test_regress/t/t_wrapper_del_context_bad.pl
new file mode 100755
index 000000000..82a4ea9cf
--- /dev/null
+++ b/test_regress/t/t_wrapper_del_context_bad.pl
@@ -0,0 +1,25 @@
+#!/usr/bin/env perl
+if (!$::Driver) { use strict; use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Multiple Model Test Module
+#
+# Copyright 2020-2021 by Andreas Kuster. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+scenarios(vlt => 1);
+
+compile(
+    make_top_shell => 0,
+    make_main => 0,
+    verilator_flags2 => ["--exe $Self->{t_dir}/$Self->{name}.cpp"],
+    );
+
+execute(
+    fails => 1,
+    expect_filename => $Self->{golden_filename},
+    );
+
+ok(1);
+1;
diff --git a/test_regress/t/t_wrapper_del_context_bad.v b/test_regress/t/t_wrapper_del_context_bad.v
new file mode 100644
index 000000000..f4ae87f02
--- /dev/null
+++ b/test_regress/t/t_wrapper_del_context_bad.v
@@ -0,0 +1,9 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2022 by Wilson Snyder.
+// SPDX-License-Identifier: CC0-1.0
+
+module top;
+   initial $finish;
+endmodule

From c8102c8ffebd3bed85f6bd0647f453ce6319f05d Mon Sep 17 00:00:00 2001
From: Geza Lore <gezalore@gmail.com>
Date: Sun, 15 May 2022 16:00:52 +0100
Subject: [PATCH 05/23] Fix typo

---
 Changes           | 2 +-
 docs/spelling.txt | 1 -
 2 files changed, 1 insertion(+), 2 deletions(-)

diff --git a/Changes b/Changes
index 615f7088f..14236dae9 100644
--- a/Changes
+++ b/Changes
@@ -248,7 +248,7 @@ Verilator 4.204 2021-06-12
 * Fix to emit 'else if' without nesting (#2944). [Geza Lore]
 * Fix part select issues in LATCH warning (#2948) (#2938). [Julien Margetts]
 * Fix to not emit empty files with low split limits (#2961). [Geza Lore]
-* Fix merging of assignments in C++ code (#2970). [Ruper Swarbrick]
+* Fix merging of assignments in C++ code (#2970). [Rupert Swarbrick]
 * Fix unused variable warnings (#2991). [Pieter Kapsenberg]
 * Fix --protect-ids when using SV classes (#2994). [Geza Lore]
 * Fix constant function calls with uninitialized value (#2995). [yanx21]
diff --git a/docs/spelling.txt b/docs/spelling.txt
index c0c5e738d..9014a6af6 100644
--- a/docs/spelling.txt
+++ b/docs/spelling.txt
@@ -257,7 +257,6 @@ Rodionov
 Rolfe
 Roodselaar
 Runtime
-Ruper
 Ruud
 Rystsov
 STandarD

From 7f1a9239abcc73aa4eca27d8d828f60f686e9dc1 Mon Sep 17 00:00:00 2001
From: Wilson Snyder <wsnyder@wsnyder.org>
Date: Sun, 15 May 2022 11:14:07 -0400
Subject: [PATCH 06/23] Commentary, fix typo (#3121)

---
 Changes | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Changes b/Changes
index 14236dae9..5c4e6c01b 100644
--- a/Changes
+++ b/Changes
@@ -14,7 +14,7 @@ Verilator 4.223 devel
 **Minor:**
 
 * Support compile time trace signal selection with tracing_on/off (#3323). [Shunyao CAD]
-* Add assert when VerilatedContext is mis-deleted (#3121). [Ruptert Swarbrick]
+* Add assert when VerilatedContext is mis-deleted (#3121). [Rupert Swarbrick]
 * Fix hang with large case statement optimization (#3405). [Mike Urbach]
 * Fix 'with' operator with type casting (#3387). [xiak95]
 

From c3c46967dcc7c196f37248416a5626b43c26801c Mon Sep 17 00:00:00 2001
From: Wilson Snyder <wsnyder@wsnyder.org>
Date: Sun, 15 May 2022 11:50:52 -0400
Subject: [PATCH 07/23] Tests: Appease sanitizer (#3121).

---
 include/verilated.h                          | 1 +
 test_regress/t/t_wrapper_del_context_bad.cpp | 4 +++-
 2 files changed, 4 insertions(+), 1 deletion(-)

diff --git a/include/verilated.h b/include/verilated.h
index aa1a582be..804d7363a 100644
--- a/include/verilated.h
+++ b/include/verilated.h
@@ -542,6 +542,7 @@ public:  // But for internal use only
 
     // Internal: Check magic number
     static void checkMagic(const VerilatedContext* contextp);
+    void selfTestClearMagic() { m_magic = 0x2; }
 };
 
 //===========================================================================
diff --git a/test_regress/t/t_wrapper_del_context_bad.cpp b/test_regress/t/t_wrapper_del_context_bad.cpp
index e6e33decd..28f80eee4 100644
--- a/test_regress/t/t_wrapper_del_context_bad.cpp
+++ b/test_regress/t/t_wrapper_del_context_bad.cpp
@@ -13,7 +13,9 @@ int main(int argc, char** argv, char** env) {
     // Create contexts
     VerilatedContext* contextp{new VerilatedContext};
 
-    delete contextp;  // Test mistake - deleting contextp
+    // Ideally we'd do this, but then address sanitizer blows up
+    // delete contextp;  // Test mistake - deleting contextp
+    contextp->selfTestClearMagic();
 
     // instantiate verilated design
     std::unique_ptr<VM_PREFIX> topp{new VM_PREFIX{contextp, "TOP"}};

From 99bdc27be323d4bd14e5d13efaffd8fdcba65c5e Mon Sep 17 00:00:00 2001
From: Wilson Snyder <wsnyder@wsnyder.org>
Date: Sun, 15 May 2022 14:26:55 -0400
Subject: [PATCH 08/23] Internals: Cleanup some statics, trivial part towards
 (#3419)

---
 include/verilated_cov.cpp    | 4 ----
 include/verilated_profiler.h | 2 +-
 include/verilated_types.h    | 4 ++--
 include/verilated_vpi.cpp    | 7 ++++---
 4 files changed, 7 insertions(+), 10 deletions(-)

diff --git a/include/verilated_cov.cpp b/include/verilated_cov.cpp
index bb1893fd8..fb0609be5 100644
--- a/include/verilated_cov.cpp
+++ b/include/verilated_cov.cpp
@@ -123,10 +123,6 @@ public:
 protected:
     friend class VerilatedCovContext;
     virtual ~VerilatedCovImp() override { clearGuts(); }
-    static VerilatedCovImp& imp() VL_MT_SAFE {
-        static VerilatedCovImp s_singleton;
-        return s_singleton;
-    }
 
 private:
     // PRIVATE METHODS
diff --git a/include/verilated_profiler.h b/include/verilated_profiler.h
index b85bd0eb5..d47be4da4 100644
--- a/include/verilated_profiler.h
+++ b/include/verilated_profiler.h
@@ -228,7 +228,7 @@ void VlPgoProfiler<T_Entries>::write(const char* modelp, const std::string& file
     // So when we have multiple models in an executable, possibly even
     // running on different threads, each will have a different symtab so
     // each will collect is own data correctly.  However when each is
-    // destroid we need to get all the data, not keep overwriting and only
+    // destroyed we need to get all the data, not keep overwriting and only
     // get the last model's data.
     static bool s_firstCall = true;
 
diff --git a/include/verilated_types.h b/include/verilated_types.h
index 8e8da1941..d45477d00 100644
--- a/include/verilated_types.h
+++ b/include/verilated_types.h
@@ -289,7 +289,7 @@ public:
     // Can't just overload operator[] or provide a "at" reference to set,
     // because we need to be able to insert only when the value is set
     T_Value& at(int32_t index) {
-        static T_Value s_throwAway;
+        static VL_THREAD_LOCAL T_Value s_throwAway;
         // Needs to work for dynamic arrays, so does not use T_MaxSize
         if (VL_UNLIKELY(index < 0 || index >= m_deque.size())) {
             s_throwAway = atDefault();
@@ -300,7 +300,7 @@ public:
     }
     // Accessing. Verilog: v = assoc[index]
     const T_Value& at(int32_t index) const {
-        static T_Value s_throwAway;
+        static VL_THREAD_LOCAL T_Value s_throwAway;
         // Needs to work for dynamic arrays, so does not use T_MaxSize
         if (VL_UNLIKELY(index < 0 || index >= m_deque.size())) {
             return atDefault();
diff --git a/include/verilated_vpi.cpp b/include/verilated_vpi.cpp
index 479a9cb59..277230720 100644
--- a/include/verilated_vpi.cpp
+++ b/include/verilated_vpi.cpp
@@ -81,8 +81,9 @@ public:
         // To simplify our free list, we use a size large enough for all derived types
         // We reserve word zero for the next pointer, as that's safer in case a
         // dangling reference to the original remains around.
-        static const size_t chunk = 96;
-        if (VL_UNCOVERABLE(size > chunk)) VL_FATAL_MT(__FILE__, __LINE__, "", "increase chunk");
+        static constexpr size_t CHUNK_SIZE = 96;
+        if (VL_UNCOVERABLE(size > CHUNK_SIZE))
+            VL_FATAL_MT(__FILE__, __LINE__, "", "increase CHUNK_SIZE");
         if (VL_LIKELY(t_freeHead)) {
             uint8_t* const newp = t_freeHead;
             t_freeHead = *(reinterpret_cast<uint8_t**>(newp));
@@ -90,7 +91,7 @@ public:
             return newp + 8;
         }
         // +8: 8 bytes for next
-        uint8_t* newp = reinterpret_cast<uint8_t*>(::operator new(chunk + 8));
+        uint8_t* newp = reinterpret_cast<uint8_t*>(::operator new(CHUNK_SIZE + 8));
         *(reinterpret_cast<uint32_t*>(newp)) = activeMagic();
         return newp + 8;
     }

From ecaa07a72a177dd6487a0b20d2ae090510d669a1 Mon Sep 17 00:00:00 2001
From: Krzysztof Bieganski <kbieganski@antmicro.com>
Date: Mon, 16 May 2022 21:44:41 +0200
Subject: [PATCH 09/23] Rename AstTimingControl to AstEventControl (#3425)

Signed-off-by: Krzysztof Bieganski <kbieganski@antmicro.com>
---
 src/V3AstNodes.h                         | 8 ++++----
 src/V3LinkParse.cpp                      | 4 ++--
 src/V3Width.cpp                          | 6 +++---
 src/verilog.y                            | 2 +-
 test_regress/t/t_event_control_unsup.out | 8 ++++----
 test_regress/t/t_lint_comb_bad.out       | 2 +-
 6 files changed, 15 insertions(+), 15 deletions(-)

diff --git a/src/V3AstNodes.h b/src/V3AstNodes.h
index 5082ae08d..80ae000cc 100644
--- a/src/V3AstNodes.h
+++ b/src/V3AstNodes.h
@@ -5243,15 +5243,15 @@ public:
     }
 };
 
-class AstTimingControl final : public AstNodeStmt {
+class AstEventControl final : public AstNodeStmt {
     // Parents: stmtlist
 public:
-    AstTimingControl(FileLine* fl, AstSenTree* sensesp, AstNode* stmtsp)
-        : ASTGEN_SUPER_TimingControl(fl) {
+    AstEventControl(FileLine* fl, AstSenTree* sensesp, AstNode* stmtsp)
+        : ASTGEN_SUPER_EventControl(fl) {
         setNOp1p(sensesp);
         setNOp2p(stmtsp);
     }
-    ASTNODE_NODE_FUNCS(TimingControl)
+    ASTNODE_NODE_FUNCS(EventControl)
     virtual string verilogKwd() const override { return "@(%l) %r"; }
     virtual bool isGateOptimizable() const override { return false; }
     virtual bool isPredictOptimizable() const override { return false; }
diff --git a/src/V3LinkParse.cpp b/src/V3LinkParse.cpp
index df1e36436..79be8fd05 100644
--- a/src/V3LinkParse.cpp
+++ b/src/V3LinkParse.cpp
@@ -582,12 +582,12 @@ private:
         iterateChildren(nodep);
         nodep->timeunit(m_modp->timeunit());
     }
-    virtual void visit(AstTimingControl* nodep) override {
+    virtual void visit(AstEventControl* nodep) override {
         cleanFileline(nodep);
         iterateChildren(nodep);
         AstAlways* const alwaysp = VN_CAST(nodep->backp(), Always);
         if (alwaysp && alwaysp->keyword() == VAlwaysKwd::ALWAYS_COMB) {
-            alwaysp->v3error("Timing control statements not legal under always_comb "
+            alwaysp->v3error("Event control statements not legal under always_comb "
                              "(IEEE 1800-2017 9.2.2.2.2)\n"
                              << nodep->warnMore() << "... Suggest use a normal 'always'");
             VL_DO_DANGLING(nodep->unlinkFrBack()->deleteTree(), nodep);
diff --git a/src/V3Width.cpp b/src/V3Width.cpp
index f5e16ec21..6118bcff4 100644
--- a/src/V3Width.cpp
+++ b/src/V3Width.cpp
@@ -1323,10 +1323,10 @@ private:
         nodep->replaceWith(newp);
         VL_DO_DANGLING(nodep->deleteTree(), nodep);
     }
-    virtual void visit(AstTimingControl* nodep) override {
-        nodep->v3warn(E_UNSUPPORTED, "Unsupported: timing control statement in this location\n"
+    virtual void visit(AstEventControl* nodep) override {
+        nodep->v3warn(E_UNSUPPORTED, "Unsupported: event control statement in this location\n"
                                          << nodep->warnMore()
-                                         << "... Suggest have one timing control statement "
+                                         << "... Suggest have one event control statement "
                                          << "per procedure, at the top of the procedure");
         VL_DO_DANGLING(nodep->unlinkFrBack()->deleteTree(), nodep);
     }
diff --git a/src/verilog.y b/src/verilog.y
index 84c778b45..3175ee9d0 100644
--- a/src/verilog.y
+++ b/src/verilog.y
@@ -3252,7 +3252,7 @@ statement_item<nodep>:          // IEEE: statement_item
         |       par_block                               { $$ = $1; }
         //                      // IEEE: procedural_timing_control_statement + procedural_timing_control
         |       delay_control stmtBlock                 { $$ = new AstDelay($1->fileline(), $1); $$->addNextNull($2); }
-        |       event_control stmtBlock                 { $$ = new AstTimingControl(FILELINE_OR_CRE($1), $1, $2); }
+        |       event_control stmtBlock                 { $$ = new AstEventControl(FILELINE_OR_CRE($1), $1, $2); }
         //UNSUP cycle_delay stmtBlock                   { UNSUP }
         //
         |       seq_block                               { $$ = $1; }
diff --git a/test_regress/t/t_event_control_unsup.out b/test_regress/t/t_event_control_unsup.out
index 1b0a26e28..7c40c182e 100644
--- a/test_regress/t/t_event_control_unsup.out
+++ b/test_regress/t/t_event_control_unsup.out
@@ -1,12 +1,12 @@
-%Error-UNSUPPORTED: t/t_event_control_unsup.v:14:7: Unsupported: timing control statement in this location
+%Error-UNSUPPORTED: t/t_event_control_unsup.v:14:7: Unsupported: event control statement in this location
                                                   : ... In instance t
-                                                  : ... Suggest have one timing control statement per procedure, at the top of the procedure
+                                                  : ... Suggest have one event control statement per procedure, at the top of the procedure
    14 |       @(clk);
       |       ^
                     ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest
-%Error-UNSUPPORTED: t/t_event_control_unsup.v:16:7: Unsupported: timing control statement in this location
+%Error-UNSUPPORTED: t/t_event_control_unsup.v:16:7: Unsupported: event control statement in this location
                                                   : ... In instance t
-                                                  : ... Suggest have one timing control statement per procedure, at the top of the procedure
+                                                  : ... Suggest have one event control statement per procedure, at the top of the procedure
    16 |       @(clk);
       |       ^
 %Error: Exiting due to
diff --git a/test_regress/t/t_lint_comb_bad.out b/test_regress/t/t_lint_comb_bad.out
index 176774ef6..ffdca1f17 100644
--- a/test_regress/t/t_lint_comb_bad.out
+++ b/test_regress/t/t_lint_comb_bad.out
@@ -1,4 +1,4 @@
-%Error: t/t_lint_comb_bad.v:14:4: Timing control statements not legal under always_comb (IEEE 1800-2017 9.2.2.2.2)
+%Error: t/t_lint_comb_bad.v:14:4: Event control statements not legal under always_comb (IEEE 1800-2017 9.2.2.2.2)
                                 : ... Suggest use a normal 'always'
    14 |    always_comb @(*) begin
       |    ^~~~~~~~~~~

From 3f7a248ed4280e51ace8a1496721a5df845806e3 Mon Sep 17 00:00:00 2001
From: Krzysztof Bieganski <kbieganski@antmicro.com>
Date: Mon, 16 May 2022 21:45:33 +0200
Subject: [PATCH 10/23] Refactor some of the Begin handling to a separate
 function (#3426)

Signed-off-by: Krzysztof Bieganski <kbieganski@antmicro.com>
---
 src/V3Begin.cpp | 51 +++++++++++++++++++++++++++----------------------
 1 file changed, 28 insertions(+), 23 deletions(-)

diff --git a/src/V3Begin.cpp b/src/V3Begin.cpp
index 75efa0f03..f2d74b678 100644
--- a/src/V3Begin.cpp
+++ b/src/V3Begin.cpp
@@ -76,6 +76,33 @@ private:
         return a + "__DOT__" + b;
     }
 
+    void dotNames(const AstNodeBlock* const nodep, const char* const blockName) {
+        UINFO(8, "nname " << m_namedScope << endl);
+        if (nodep->name() != "") {  // Else unneeded unnamed block
+            // Create data for dotted variable resolution
+            string dottedname = nodep->name() + "__DOT__";  // So always found
+            string::size_type pos;
+            while ((pos = dottedname.find("__DOT__")) != string::npos) {
+                const string ident = dottedname.substr(0, pos);
+                dottedname = dottedname.substr(pos + strlen("__DOT__"));
+                if (nodep->name() != "") {
+                    m_displayScope = dot(m_displayScope, ident);
+                    m_namedScope = dot(m_namedScope, ident);
+                }
+                m_unnamedScope = dot(m_unnamedScope, ident);
+                // Create CellInline for dotted var resolution
+                if (!m_ftaskp) {
+                    AstCellInline* const inlinep = new AstCellInline(
+                        nodep->fileline(), m_unnamedScope, blockName, m_modp->timeunit());
+                    m_modp->addInlinesp(inlinep);  // Must be parsed before any AstCells
+                }
+            }
+        }
+
+        // Remap var names and replace lower Begins
+        iterateAndNextNull(nodep->stmtsp());
+    }
+
     void liftNode(AstNode* nodep) {
         nodep->unlinkFrBack();
         if (m_ftaskp) {
@@ -141,30 +168,8 @@ private:
         VL_RESTORER(m_namedScope);
         VL_RESTORER(m_unnamedScope);
         {
-            UINFO(8, "nname " << m_namedScope << endl);
-            if (nodep->name() != "") {  // Else unneeded unnamed block
-                // Create data for dotted variable resolution
-                string dottedname = nodep->name() + "__DOT__";  // So always found
-                string::size_type pos;
-                while ((pos = dottedname.find("__DOT__")) != string::npos) {
-                    const string ident = dottedname.substr(0, pos);
-                    dottedname = dottedname.substr(pos + strlen("__DOT__"));
-                    if (nodep->name() != "") {
-                        m_displayScope = dot(m_displayScope, ident);
-                        m_namedScope = dot(m_namedScope, ident);
-                    }
-                    m_unnamedScope = dot(m_unnamedScope, ident);
-                    // Create CellInline for dotted var resolution
-                    if (!m_ftaskp) {
-                        AstCellInline* const inlinep = new AstCellInline(
-                            nodep->fileline(), m_unnamedScope, "__BEGIN__", m_modp->timeunit());
-                        m_modp->addInlinesp(inlinep);  // Must be parsed before any AstCells
-                    }
-                }
-            }
+            dotNames(nodep, "__BEGIN__");
 
-            // Remap var names and replace lower Begins
-            iterateAndNextNull(nodep->stmtsp());
             UASSERT_OBJ(!nodep->genforp(), nodep, "GENFORs should have been expanded earlier");
 
             // Cleanup

From 561eaa311de62df59e7d7339fc7a77ca76606abc Mon Sep 17 00:00:00 2001
From: Krzysztof Bieganski <kbieganski@antmicro.com>
Date: Tue, 17 May 2022 15:19:06 +0200
Subject: [PATCH 11/23] Tests: Enable CI testing with GCC 10 (#3432)

This is a pre-PR to #3363.

Signed-off-by: Krzysztof Bieganski <kbieganski@antmicro.com>
---
 .github/workflows/build.yml | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/.github/workflows/build.yml b/.github/workflows/build.yml
index 4cced10dc..47b5f70b2 100644
--- a/.github/workflows/build.yml
+++ b/.github/workflows/build.yml
@@ -40,6 +40,11 @@ jobs:
           - m32: ${{ github.event_name == 'pull_request' && 1              || 'do-not-exclude' }}
           # Build -m32 only on ubuntu-20.04
           - {os: ubuntu-18.04, m32: 1}
+        include:
+          # Build GCC 10 on ubuntu-20.04
+          - os: ubuntu-20.04
+            compiler: { cc: gcc-10, cxx: g++-10 }
+            m32: 0
     runs-on: ${{ matrix.os }}
     name: Build | ${{ matrix.os }} | ${{ matrix.compiler.cc }} ${{ matrix.m32 && '| -m32' || '' }}
     env:
@@ -102,6 +107,13 @@ jobs:
           - m32: ${{ github.event_name == 'pull_request' && 1              || 'do-not-exclude' }}
           # Build -m32 only on ubuntu-20.04
           - {os: ubuntu-18.04, m32: 1}
+        include:
+          # Test with GCC 10 on ubuntu-20.04 without m32
+          - {os: ubuntu-20.04, compiler: { cc: gcc-10, cxx: g++-10 }, m32: 0, suite: dist-vlt-0}
+          - {os: ubuntu-20.04, compiler: { cc: gcc-10, cxx: g++-10 }, m32: 0, suite: dist-vlt-1}
+          - {os: ubuntu-20.04, compiler: { cc: gcc-10, cxx: g++-10 }, m32: 0, suite: dist-vlt-2}
+          - {os: ubuntu-20.04, compiler: { cc: gcc-10, cxx: g++-10 }, m32: 0, suite: vltmt-0}
+          - {os: ubuntu-20.04, compiler: { cc: gcc-10, cxx: g++-10 }, m32: 0, suite: vltmt-1}
     runs-on: ${{ matrix.os }}
     name: Test | ${{ matrix.os }} | ${{ matrix.compiler.cc }} | ${{ matrix.suite }} ${{ matrix.m32 && '| -m32' || '' }}
     env:

From 67bb2c640ef4887b4798c066177b09fe8fb5c94a Mon Sep 17 00:00:00 2001
From: Krzysztof Bieganski <kbieganski@antmicro.com>
Date: Tue, 17 May 2022 15:19:51 +0200
Subject: [PATCH 12/23] Tests: Rename t_timing_clkgen to t_timing_clkgen1
 (#3430)

This is a pre-PR to #3363, which will introduce more clock gen tests.

Signed-off-by: Krzysztof Bieganski <kbieganski@antmicro.com>
---
 test_regress/t/{t_timing_clkgen.pl => t_timing_clkgen1.pl} | 0
 test_regress/t/{t_timing_clkgen.v => t_timing_clkgen1.v}   | 0
 2 files changed, 0 insertions(+), 0 deletions(-)
 rename test_regress/t/{t_timing_clkgen.pl => t_timing_clkgen1.pl} (100%)
 rename test_regress/t/{t_timing_clkgen.v => t_timing_clkgen1.v} (100%)

diff --git a/test_regress/t/t_timing_clkgen.pl b/test_regress/t/t_timing_clkgen1.pl
similarity index 100%
rename from test_regress/t/t_timing_clkgen.pl
rename to test_regress/t/t_timing_clkgen1.pl
diff --git a/test_regress/t/t_timing_clkgen.v b/test_regress/t/t_timing_clkgen1.v
similarity index 100%
rename from test_regress/t/t_timing_clkgen.v
rename to test_regress/t/t_timing_clkgen1.v

From 0a91ddf38a2d585868a54338e28923b92b07b39b Mon Sep 17 00:00:00 2001
From: Krzysztof Bieganski <kbieganski@antmicro.com>
Date: Tue, 17 May 2022 15:20:59 +0200
Subject: [PATCH 13/23] Tests: Better grep check in t_foreach (#3435)

This is a pre-PR to #3363.

Signed-off-by: Krzysztof Bieganski <kbieganski@antmicro.com>
---
 test_regress/t/t_foreach.pl | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/test_regress/t/t_foreach.pl b/test_regress/t/t_foreach.pl
index cb80916f1..3ff192bbd 100755
--- a/test_regress/t/t_foreach.pl
+++ b/test_regress/t/t_foreach.pl
@@ -28,7 +28,7 @@ for my $file (glob_all("$Self->{obj_dir}/$Self->{VM_PREFIX}*.cpp")) {
 # have been evaluated inside the compiler. So there should be
 # no references to 'sum' in the .cpp.
 for my $file (glob_all("$Self->{obj_dir}/$Self->{VM_PREFIX}*.cpp")) {
-    file_grep_not($file, qr/sum/);
+    file_grep_not($file, qr/[^a-zA-Z]sum[^a-zA-Z]/);
 }
 
 ok(1);

From e018eb7bacbc8095cd33fa0ef0dd1a7494453a9d Mon Sep 17 00:00:00 2001
From: Krzysztof Bieganski <kbieganski@antmicro.com>
Date: Tue, 17 May 2022 15:22:43 +0200
Subject: [PATCH 14/23] Support AstClass::repairCache() after V3Class (#3431)

This is a pre-PR to #3363.

Signed-off-by: Krzysztof Bieganski <kbieganski@antmicro.com>
---
 src/V3AstNodes.cpp | 12 ++++++++++--
 src/V3Class.cpp    |  1 +
 2 files changed, 11 insertions(+), 2 deletions(-)

diff --git a/src/V3AstNodes.cpp b/src/V3AstNodes.cpp
index fc6999853..33d275e4e 100644
--- a/src/V3AstNodes.cpp
+++ b/src/V3AstNodes.cpp
@@ -1309,7 +1309,8 @@ void AstClassPackage::cloneRelink() {
 }
 void AstClass::insertCache(AstNode* nodep) {
     const bool doit = (VN_IS(nodep, Var) || VN_IS(nodep, EnumItemRef)
-                       || (VN_IS(nodep, NodeFTask) && !VN_AS(nodep, NodeFTask)->isExternProto()));
+                       || (VN_IS(nodep, NodeFTask) && !VN_AS(nodep, NodeFTask)->isExternProto())
+                       || VN_IS(nodep, CFunc));
     if (doit) {
         if (m_members.find(nodep->name()) != m_members.end()) {
             nodep->v3error("Duplicate declaration of member name: " << nodep->prettyNameQ());
@@ -1320,7 +1321,14 @@ void AstClass::insertCache(AstNode* nodep) {
 }
 void AstClass::repairCache() {
     clearCache();
-    for (AstNode* itemp = membersp(); itemp; itemp = itemp->nextp()) { insertCache(itemp); }
+    for (auto* itemp = membersp(); itemp; itemp = itemp->nextp()) {
+        if (const auto* const scopep = VN_CAST(itemp, Scope)) {
+            for (auto* itemp = scopep->blocksp(); itemp; itemp = itemp->nextp())
+                insertCache(itemp);
+        } else {
+            insertCache(itemp);
+        }
+    }
 }
 bool AstClass::isClassExtendedFrom(const AstClass* refClassp, const AstClass* baseClassp) {
     // TAIL RECURSIVE
diff --git a/src/V3Class.cpp b/src/V3Class.cpp
index 6a7a3ce4f..5b29eccd6 100644
--- a/src/V3Class.cpp
+++ b/src/V3Class.cpp
@@ -97,6 +97,7 @@ private:
             m_prefix = nodep->name() + "__02e";  // .
             iterateChildren(nodep);
         }
+        nodep->repairCache();
     }
     virtual void visit(AstNodeModule* nodep) override {
         // Visit for NodeModules that are not AstClass (AstClass is-a AstNodeModule)

From 1a056f6db9e6ed74f0912ec30b8031c4336d51a6 Mon Sep 17 00:00:00 2001
From: Geza Lore <gezalore@gmail.com>
Date: Sun, 15 May 2022 16:34:04 +0100
Subject: [PATCH 15/23] Fix invalid conditional merging when starting at 'c = c
 ? a : b'

Fixes #3409.
---
 src/V3MergeCond.cpp                     | 26 ++++---
 test_regress/t/t_merge_cond_bug_3409.pl | 29 ++++++++
 test_regress/t/t_merge_cond_bug_3409.v  | 93 +++++++++++++++++++++++++
 3 files changed, 139 insertions(+), 9 deletions(-)
 create mode 100755 test_regress/t/t_merge_cond_bug_3409.pl
 create mode 100644 test_regress/t/t_merge_cond_bug_3409.v

diff --git a/src/V3MergeCond.cpp b/src/V3MergeCond.cpp
index 77b2ea935..673326f27 100644
--- a/src/V3MergeCond.cpp
+++ b/src/V3MergeCond.cpp
@@ -382,15 +382,24 @@ private:
         return false;
     }
 
-    void addToList(AstNode* nodep, AstNode* condp, int line) {
+    bool addToList(AstNode* nodep, AstNode* condp, int line) {
         // Set up head of new list if node is first in list
         if (!m_mgFirstp) {
             UASSERT_OBJ(condp, nodep, "Cannot start new list without condition " << line);
+            // Mark variable references in the condition
+            condp->foreach<AstVarRef>([](const AstVarRef* nodep) { nodep->varp()->user1(1); });
+            // Now check again if mergeable. We need this to pick up assignments to conditions,
+            // e.g.: 'c = c ? a : b' at the beginning of the list, which is in fact not mergeable
+            // because it updates the condition. We simply bail on these.
+            if (m_checkMergeable(nodep) != Mergeable::YES) {
+                // Clear marked variables
+                AstNode::user1ClearTree();
+                // We did not add to the list
+                return false;
+            }
             m_mgFirstp = nodep;
             m_mgCondp = condp;
             m_listLenght = 0;
-            // Mark variable references in the condition
-            condp->foreach<AstVarRef>([](const AstVarRef* nodep) { nodep->varp()->user1(1); });
             // Add any preceding nodes to the list that would allow us to extend the merge range
             for (;;) {
                 AstNode* const backp = m_mgFirstp->backp();
@@ -416,6 +425,8 @@ private:
         m_mgNextp = nodep->nextp();
         // If last under parent, done with current list
         if (!m_mgNextp) mergeEnd(__LINE__);
+        // We did add to the list
+        return true;
     }
 
     // If this node is the next expected node and is helpful to add to the list, do so,
@@ -424,13 +435,10 @@ private:
         UASSERT_OBJ(m_mgFirstp, nodep, "List must be open");
         if (m_mgNextp == nodep) {
             if (isSimplifiableNode(nodep)) {
-                addToList(nodep, nullptr, __LINE__);
-                return true;
-            }
-            if (isCheapNode(nodep)) {
+                if (addToList(nodep, nullptr, __LINE__)) return true;
+            } else if (isCheapNode(nodep)) {
                 nodep->user2(1);
-                addToList(nodep, nullptr, __LINE__);
-                return true;
+                if (addToList(nodep, nullptr, __LINE__)) return true;
             }
         }
         // Not added to list, so we are done with the current list
diff --git a/test_regress/t/t_merge_cond_bug_3409.pl b/test_regress/t/t_merge_cond_bug_3409.pl
new file mode 100755
index 000000000..bb6c1fab4
--- /dev/null
+++ b/test_regress/t/t_merge_cond_bug_3409.pl
@@ -0,0 +1,29 @@
+#!/usr/bin/env perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2022 by Geza Lore. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+scenarios(simulator => 1);
+
+compile(
+    verilator_flags2=> ["--stats"]
+    );
+
+execute();
+
+if ($Self->{vlt_all}) {
+    file_grep($Self->{stats}, qr/Optimizations, MergeCond merges\s+(\d+)/i,
+              0);
+    file_grep($Self->{stats}, qr/Optimizations, MergeCond merged items\s+(\d+)/i,
+              0);
+    file_grep($Self->{stats}, qr/Optimizations, MergeCond longest merge\s+(\d+)/i,
+              0);
+}
+
+ok(1);
+1;
diff --git a/test_regress/t/t_merge_cond_bug_3409.v b/test_regress/t/t_merge_cond_bug_3409.v
new file mode 100644
index 000000000..71e0ccf48
--- /dev/null
+++ b/test_regress/t/t_merge_cond_bug_3409.v
@@ -0,0 +1,93 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2022 by Raynard Qiao.
+// SPDX-License-Identifier: CC0-1.0
+
+module t(/*AUTOARG*/
+   // Inputs
+   clk
+   );
+   input clk;
+
+   integer cyc = 0;
+   reg [63:0] crc;
+   reg [63:0] sum;
+
+   // Take CRC data and apply to testblock inputs
+   wire [3:0] din = crc[3:0];
+
+   /*AUTOWIRE*/
+   // Beginning of automatic wires (for undeclared instantiated-module outputs)
+   wire                 row_found;              // From test of Test.v
+   wire [1:0]           row_idx;                // From test of Test.v
+   // End of automatics
+
+   Test test(/*AUTOINST*/
+             // Outputs
+             .row_idx                   (row_idx[1:0]),
+             .row_found                 (row_found),
+             // Inputs
+             .din                       (din));
+
+   // Aggregate outputs into a single result vector
+   wire [63:0] result = {48'b0, din, 7'b0, row_found, 2'b0, row_idx};
+
+   // Test loop
+   always @ (posedge clk) begin
+`ifdef TEST_VERBOSE
+      $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result);
+`endif
+      cyc <= cyc + 1;
+      crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
+      sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]};
+      if (cyc == 0) begin
+         // Setup
+         crc <= 64'h5aef0c8d_d70a4497;
+         sum <= '0;
+      end
+      else if (cyc < 10) begin
+         sum <= '0;
+      end
+      else if (cyc == 99) begin
+         $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum);
+         if (crc !== 64'hc77bb9b3784ea091) $stop;
+         // What checksum will we end up with (above print should match)
+`define EXPECTED_SUM 64'h8b61595b704e511f
+         if (sum !== `EXPECTED_SUM) $stop;
+         $write("*-* All Finished *-*\n");
+         $finish;
+      end
+   end
+
+endmodule
+
+module Test(/*AUTOARG*/
+   // Outputs
+   row_idx, row_found,
+   // Inputs
+   din
+   );
+
+   input din;
+   output [1:0] row_idx;
+   output       row_found;
+
+   reg [3:0]    din;
+   reg [3:0]    wide_din;
+   reg          row_found;
+   reg [1:0]    row_idx;
+
+   always_comb begin
+      integer x;
+      row_idx = {2{1'b0}};
+      row_found = 1'b0;
+      // Bug #3409: After unrolling, these conditionals should not be merged
+      // as row_found is assigned.
+      for (x = 0; $unsigned(x) < 4; x = x + 1) begin
+         row_idx = !row_found ? x[1:0] : row_idx;
+         row_found = !row_found ? din[x] : row_found;
+      end
+   end
+
+endmodule

From 9edccfdffa3ea180bf9429bb50d52ac5e436ba4f Mon Sep 17 00:00:00 2001
From: Krzysztof Bieganski <kbieganski@antmicro.com>
Date: Tue, 17 May 2022 20:19:44 +0200
Subject: [PATCH 16/23] Initial support for intra-assignment timing controls,
 net delays (#3427)

This is a pre-PR to #3363.

Signed-off-by: Krzysztof Bieganski <kbieganski@antmicro.com>
---
 src/V3Ast.h                                   |   7 +-
 src/V3AstNodes.h                              |  18 ++-
 src/V3ParseGrammar.cpp                        |   2 +
 src/V3Width.cpp                               |   6 +
 src/verilog.y                                 | 106 ++++++++++--------
 test_regress/t/t_delay_stmtdly_bad.out        |  14 ++-
 test_regress/t/t_gate_delay_unsup.out         |  12 ++
 test_regress/t/t_gate_delay_unsup.pl          |  22 ++++
 .../t/t_timing_intra_assign_delay.out         |  31 +++++
 test_regress/t/t_timing_intra_assign_delay.pl |  20 ++++
 test_regress/t/t_timing_intra_assign_delay.v  |  24 ++++
 .../t/t_timing_intra_assign_event.out         |  32 ++++++
 test_regress/t/t_timing_intra_assign_event.pl |  20 ++++
 test_regress/t/t_timing_intra_assign_event.v  |  34 ++++++
 test_regress/t/t_timing_net_delay.out         |  11 ++
 test_regress/t/t_timing_net_delay.pl          |  20 ++++
 test_regress/t/t_timing_net_delay.v           |  30 +++++
 17 files changed, 351 insertions(+), 58 deletions(-)
 create mode 100644 test_regress/t/t_gate_delay_unsup.out
 create mode 100755 test_regress/t/t_gate_delay_unsup.pl
 create mode 100644 test_regress/t/t_timing_intra_assign_delay.out
 create mode 100755 test_regress/t/t_timing_intra_assign_delay.pl
 create mode 100644 test_regress/t/t_timing_intra_assign_delay.v
 create mode 100644 test_regress/t/t_timing_intra_assign_event.out
 create mode 100755 test_regress/t/t_timing_intra_assign_event.pl
 create mode 100644 test_regress/t/t_timing_intra_assign_event.v
 create mode 100644 test_regress/t/t_timing_net_delay.out
 create mode 100755 test_regress/t/t_timing_net_delay.pl
 create mode 100644 test_regress/t/t_timing_net_delay.v

diff --git a/src/V3Ast.h b/src/V3Ast.h
index ca00b8040..47ae4dcc0 100644
--- a/src/V3Ast.h
+++ b/src/V3Ast.h
@@ -2488,10 +2488,12 @@ public:
 
 class AstNodeAssign VL_NOT_FINAL : public AstNodeStmt {
 protected:
-    AstNodeAssign(VNType t, FileLine* fl, AstNode* lhsp, AstNode* rhsp)
+    AstNodeAssign(VNType t, FileLine* fl, AstNode* lhsp, AstNode* rhsp,
+                  AstNode* timingControlp = nullptr)
         : AstNodeStmt{t, fl} {
         setOp1p(rhsp);
         setOp2p(lhsp);
+        addNOp3p(timingControlp);
         dtypeFrom(lhsp);
     }
 
@@ -2502,6 +2504,9 @@ public:
     // So iteration hits the RHS which is "earlier" in execution order, it's op1, not op2
     AstNode* rhsp() const { return op1p(); }  // op1 = Assign from
     AstNode* lhsp() const { return op2p(); }  // op2 = Assign to
+    // op3 = Timing controls (delays, event controls)
+    AstNode* timingControlp() const { return op3p(); }
+    void addTimingControlp(AstNode* const np) { addNOp3p(np); }
     void rhsp(AstNode* np) { setOp1p(np); }
     void lhsp(AstNode* np) { setOp2p(np); }
     virtual bool hasDType() const override { return true; }
diff --git a/src/V3AstNodes.h b/src/V3AstNodes.h
index 80ae000cc..404eff633 100644
--- a/src/V3AstNodes.h
+++ b/src/V3AstNodes.h
@@ -2142,6 +2142,9 @@ public:
     virtual AstNodeDType* getChildDTypep() const override { return childDTypep(); }
     // op1 = Range of variable
     AstNodeDType* childDTypep() const { return VN_AS(op1p(), NodeDType); }
+    // op2 = Net delay
+    AstNode* delayp() const { return op2p(); }
+    void delayp(AstNode* const nodep) { setNOp2p(nodep); }
     AstNodeDType* dtypeSkipRefp() const { return subDTypep()->skipRefp(); }
     // (Slow) recurse down to find basic data type (Note don't need virtual -
     // AstVar isn't a NodeDType)
@@ -3481,8 +3484,8 @@ public:
 
 class AstAssign final : public AstNodeAssign {
 public:
-    AstAssign(FileLine* fl, AstNode* lhsp, AstNode* rhsp)
-        : ASTGEN_SUPER_Assign(fl, lhsp, rhsp) {
+    AstAssign(FileLine* fl, AstNode* lhsp, AstNode* rhsp, AstNode* timingControlp = nullptr)
+        : ASTGEN_SUPER_Assign(fl, lhsp, rhsp, timingControlp) {
         dtypeFrom(lhsp);
     }
     ASTNODE_NODE_FUNCS(Assign)
@@ -3507,8 +3510,8 @@ public:
 
 class AstAssignDly final : public AstNodeAssign {
 public:
-    AstAssignDly(FileLine* fl, AstNode* lhsp, AstNode* rhsp)
-        : ASTGEN_SUPER_AssignDly(fl, lhsp, rhsp) {}
+    AstAssignDly(FileLine* fl, AstNode* lhsp, AstNode* rhsp, AstNode* timingControlp = nullptr)
+        : ASTGEN_SUPER_AssignDly(fl, lhsp, rhsp, timingControlp) {}
     ASTNODE_NODE_FUNCS(AssignDly)
     virtual AstNode* cloneType(AstNode* lhsp, AstNode* rhsp) override {
         return new AstAssignDly(this->fileline(), lhsp, rhsp);
@@ -3817,15 +3820,18 @@ public:
 class AstDelay final : public AstNodeStmt {
     // Delay statement
 public:
-    AstDelay(FileLine* fl, AstNode* lhsp)
+    AstDelay(FileLine* fl, AstNode* lhsp, AstNode* stmtsp)
         : ASTGEN_SUPER_Delay(fl) {
         setOp1p(lhsp);
+        setNOp2p(stmtsp);
     }
     ASTNODE_NODE_FUNCS(Delay)
     virtual bool same(const AstNode* samep) const override { return true; }
     //
-    AstNode* lhsp() const { return op1p(); }  // op2 = Statements to evaluate
+    AstNode* lhsp() const { return op1p(); }  // op1 = delay value
     void lhsp(AstNode* nodep) { setOp1p(nodep); }
+    void stmtsp(AstNode* nodep) { setOp2p(nodep); }  // op2 = statements under delay
+    AstNode* stmtsp() const { return op2p(); }
 };
 
 class AstGenCase final : public AstNodeCase {
diff --git a/src/V3ParseGrammar.cpp b/src/V3ParseGrammar.cpp
index 3f3d06909..2cc65af6a 100644
--- a/src/V3ParseGrammar.cpp
+++ b/src/V3ParseGrammar.cpp
@@ -189,6 +189,8 @@ AstVar* V3ParseGrammar::createVariable(FileLine* fileline, const string& name,
     nodep->ansi(m_pinAnsi);
     nodep->declTyped(m_varDeclTyped);
     nodep->lifetime(m_varLifetime);
+    nodep->delayp(m_netDelayp);
+    m_netDelayp = nullptr;
     if (GRAMMARP->m_varDecl != VVarType::UNKNOWN) nodep->combineType(GRAMMARP->m_varDecl);
     if (GRAMMARP->m_varIO != VDirection::NONE) {
         nodep->declDirection(GRAMMARP->m_varIO);
diff --git a/src/V3Width.cpp b/src/V3Width.cpp
index 6118bcff4..69cee08f6 100644
--- a/src/V3Width.cpp
+++ b/src/V3Width.cpp
@@ -595,6 +595,7 @@ private:
             VL_DO_DANGLING(pushDeletep(nodep->unlinkFrBack()), nodep);
             return;
         }
+        if (nodep->stmtsp()) nodep->addNextHere(nodep->stmtsp()->unlinkFrBack());
         nodep->v3warn(STMTDLY, "Unsupported: Ignoring delay on this delayed statement.");
         VL_DO_DANGLING(pushDeletep(nodep->unlinkFrBack()), nodep);
     }
@@ -3984,6 +3985,11 @@ private:
                 nodep->v3warn(E_UNSUPPORTED, "Unsupported: assignment of event data type");
             }
         }
+        if (nodep->timingControlp()) {
+            nodep->timingControlp()->v3warn(
+                ASSIGNDLY, "Unsupported: Ignoring timing control on this assignment.");
+            nodep->timingControlp()->unlinkFrBackWithNext()->deleteTree();
+        }
         if (VN_IS(nodep->rhsp(), EmptyQueue)) {
             UINFO(9, "= {} -> .delete(): " << nodep);
             if (!VN_IS(nodep->lhsp()->dtypep()->skipRefp(), QueueDType)) {
diff --git a/src/verilog.y b/src/verilog.y
index 3175ee9d0..a31704545 100644
--- a/src/verilog.y
+++ b/src/verilog.y
@@ -40,6 +40,13 @@
 #define BBUNSUP(fl, msg) (fl)->v3warn(E_UNSUPPORTED, msg)
 #define GATEUNSUP(fl, tok) \
     { BBUNSUP((fl), "Unsupported: Verilog 1995 gate primitive: " << (tok)); }
+#define PRIMDLYUNSUP(nodep) \
+    { \
+        if (nodep) { \
+            nodep->v3warn(ASSIGNDLY, "Unsupported: Ignoring delay on this primitive."); \
+            nodep->deleteTree(); \
+        } \
+    }
 
 //======================================================================
 // Statics (for here only)
@@ -60,6 +67,7 @@ public:
     AstCase* m_caseAttrp = nullptr;  // Current case statement for attribute adding
     AstNodeDType* m_varDTypep = nullptr;  // Pointer to data type for next signal declaration
     AstNodeDType* m_memDTypep = nullptr;  // Pointer to data type for next member declaration
+    AstNode* m_netDelayp = nullptr;  // Pointer to delay for next signal declaration
     AstNodeModule* m_modp = nullptr;  // Last module for timeunits
     bool m_pinAnsi = false;  // In ANSI port list
     FileLine* m_instModuleFl = nullptr;  // Fileline of module referenced for instantiations
@@ -138,6 +146,7 @@ public:
         if (m_varDTypep) VL_DO_CLEAR(m_varDTypep->deleteTree(), m_varDTypep = nullptr);
         m_varDTypep = dtypep;
     }
+    void setNetDelay(AstNode* netDelayp) { m_netDelayp = netDelayp; }
     void pinPush() {
         m_pinStack.push(m_pinNum);
         m_pinNum = 1;
@@ -1708,11 +1717,13 @@ net_dataTypeE<nodeDTypep>:
                 var_data_type                           { $$ = $1; }
         |       signingE rangeList delayE
                         { $$ = GRAMMARP->addRange(new AstBasicDType{$2->fileline(), LOGIC, $1},
-                                                                    $2, true); }  // not implicit
+                                                                    $2, true);
+                          GRAMMARP->setNetDelay($3); }  // not implicit
         |       signing
                         { $$ = new AstBasicDType{$<fl>1, LOGIC, $1}; }  // not implicit
         |       /*implicit*/ delayE
-                        { $$ = new AstBasicDType{CRELINE(), LOGIC}; }  // not implicit
+                        { $$ = new AstBasicDType{CRELINE(), LOGIC};
+                          GRAMMARP->setNetDelay($1); }  // not implicit
         ;
 
 net_type:                       // ==IEEE: net_type
@@ -2389,7 +2400,15 @@ module_common_item<nodep>:      // ==IEEE: module_common_item
         ;
 
 continuous_assign<nodep>:       // IEEE: continuous_assign
-                yASSIGN strengthSpecE delayE assignList ';'     { $$ = $4; }
+                yASSIGN strengthSpecE delayE assignList ';'
+                {
+                    $$ = $4;
+                    if ($3)
+                        for (auto* nodep = $$; nodep; nodep = nodep->nextp()) {
+                            auto* const assignp = VN_AS(nodep, NodeAssign);
+                            assignp->addTimingControlp(nodep == $$ ? $3 : $3->cloneTree(false));
+                        }
+                }
         ;
 
 initial_construct<nodep>:       // IEEE: initial_construct
@@ -2630,22 +2649,21 @@ assignOne<nodep>:
                 variable_lvalue '=' expr                { $$ = new AstAssignW($2,$1,$3); }
         ;
 
-//UNSUPdelay_or_event_controlE<nodep>:  // IEEE: delay_or_event_control plus empty
-//UNSUP         /* empty */                             { $$ = nullptr; }
-//UNSUP |       delay_control                           { $$ = $1; }
-//UNSUP |       event_control                           { $$ = $1; }
+delay_or_event_controlE<nodep>:  // IEEE: delay_or_event_control plus empty
+                /* empty */                             { $$ = nullptr; }
+        |       delay_control                           { $$ = $1; }
+        |       event_control                           { $$ = $1; }
 //UNSUP |       yREPEAT '(' expr ')' event_control      { }
-//UNSUP ;
-
-delayE:
-                /* empty */                             { }
-        |       delay                                   { }
         ;
 
-delay:
+delayE<nodep>:
+                /* empty */                             { $$ = nullptr; }
+        |       delay                                   { $$ = $1; }
+        ;
+
+delay<nodep>:
                 delay_control
-                        { $1->v3warn(ASSIGNDLY, "Unsupported: Ignoring delay on this assignment/primitive.");
-                          DEL($1); }
+                        { $$ = $1; }
         ;
 
 delay_control<nodep>:   //== IEEE: delay_control
@@ -2682,8 +2700,9 @@ netSig<varp>:                   // IEEE: net_decl_assignment -  one element from
                         { $$ = VARDONEA($<fl>1,*$1, nullptr, $2); }
         |       netId sigAttrListE '=' expr
                         { $$ = VARDONEA($<fl>1, *$1, nullptr, $2);
-                          $$->addNext(new AstAssignW{$3, new AstVarRef{$<fl>1, *$1, VAccess::WRITE}, $4}); }
-        |       netId variable_dimensionList sigAttrListE
+                          auto* const assignp = new AstAssignW{$3, new AstVarRef{$<fl>1, *$1, VAccess::WRITE}, $4};
+                          if ($$->delayp()) assignp->addTimingControlp($$->delayp()->unlinkFrBack());  // IEEE 1800-2017 10.3.3
+                          $$->addNext(assignp); }        |       netId variable_dimensionList sigAttrListE
                         { $$ = VARDONEA($<fl>1,*$1, $2, $3); }
         ;
 
@@ -3141,12 +3160,10 @@ statement_item<nodep>:          // IEEE: statement_item
         |       fexprLvalue '=' dynamic_array_new ';'   { $$ = new AstAssign($2, $1, $3); }
         //
         //                      // IEEE: nonblocking_assignment
-        |       fexprLvalue yP_LTE delayE expr ';'      { $$ = new AstAssignDly($2,$1,$4); }
-        //UNSUP fexprLvalue yP_LTE delay_or_event_controlE expr ';'     { UNSUP }
-        //
-        //                      // IEEE: procedural_continuous_assignment
-        |       yASSIGN idClassSel '=' delayE expr ';'  { $$ = new AstAssign($1,$2,$5); }
-        //UNSUP:                        delay_or_event_controlE above
+        |       fexprLvalue yP_LTE delay_or_event_controlE expr ';'
+                        { $$ = new AstAssignDly{$2, $1, $4, $3}; }
+        |       yASSIGN idClassSel '=' delay_or_event_controlE expr ';'
+                        { $$ = new AstAssign{$1, $2, $5, $4}; }
         |       yDEASSIGN variable_lvalue ';'
                         { $$ = nullptr; BBUNSUP($1, "Unsupported: Verilog 1995 deassign"); }
         |       yFORCE variable_lvalue '=' expr ';'
@@ -3224,10 +3241,8 @@ statement_item<nodep>:          // IEEE: statement_item
                         { // AssignDly because we don't have stratified queue, and need to
                           // read events, clear next event, THEN apply this set
                           $$ = new AstAssignDly($1, $2, new AstConst($1, AstConst::BitTrue())); }
-        //UNSUP yP_MINUSGTGT delay_or_event_controlE hierarchical_identifier/*event*/ ';'       { UNSUP }
-        //                      // IEEE remove below
-        |       yP_MINUSGTGT delayE idDotted/*hierarchical_identifier-event*/ ';'
-                        { $$ = new AstAssignDly($1, $3, new AstConst($1, AstConst::BitTrue())); }
+        |       yP_MINUSGTGT delay_or_event_controlE idDotted/*hierarchical_identifier-event*/ ';'
+                        { $$ = new AstAssignDly{$1, $3, new AstConst{$1, AstConst::BitTrue()}, $2}; }
         //
         //                      // IEEE: loop_statement
         |       yFOREVER stmtBlock                      { $$ = new AstWhile($1,new AstConst($1, AstConst::BitTrue()), $2); }
@@ -3251,7 +3266,7 @@ statement_item<nodep>:          // IEEE: statement_item
         //
         |       par_block                               { $$ = $1; }
         //                      // IEEE: procedural_timing_control_statement + procedural_timing_control
-        |       delay_control stmtBlock                 { $$ = new AstDelay($1->fileline(), $1); $$->addNextNull($2); }
+        |       delay_control stmtBlock                 { $$ = new AstDelay{$1->fileline(), $1, $2}; }
         |       event_control stmtBlock                 { $$ = new AstEventControl(FILELINE_OR_CRE($1), $1, $2); }
         //UNSUP cycle_delay stmtBlock                   { UNSUP }
         //
@@ -3313,11 +3328,10 @@ statementVerilatorPragmas<nodep>:
 //UNSUP ;
 
 foperator_assignment<nodep>:    // IEEE: operator_assignment (for first part of expression)
-                fexprLvalue '=' delayE expr     { $$ = new AstAssign($2,$1,$4); }
+                fexprLvalue '=' delay_or_event_controlE expr    { $$ = new AstAssign{$2, $1, $4, $3}; }
         |       fexprLvalue '=' yD_FOPEN '(' expr ')'           { $$ = new AstFOpenMcd($3,$1,$5); }
         |       fexprLvalue '=' yD_FOPEN '(' expr ',' expr ')'  { $$ = new AstFOpen($3,$1,$5,$7); }
         //
-        //UNSUP ~f~exprLvalue '=' delay_or_event_controlE expr { UNSUP }
         //UNSUP ~f~exprLvalue yP_PLUS(etc) expr         { UNSUP }
         |       fexprLvalue yP_PLUSEQ    expr           { $$ = new AstAssign($2,$1,new AstAdd    ($2,$1->cloneTree(true),$3)); }
         |       fexprLvalue yP_MINUSEQ   expr           { $$ = new AstAssign($2,$1,new AstSub    ($2,$1->cloneTree(true),$3)); }
@@ -4687,22 +4701,22 @@ stream_expressionOrDataType<nodep>:     // IEEE: from streaming_concatenation
 // Gate declarations
 
 gateDecl<nodep>:
-                yBUF    delayE gateBufList ';'          { $$ = $3; }
-        |       yBUFIF0 delayE gateBufif0List ';'       { $$ = $3; }
-        |       yBUFIF1 delayE gateBufif1List ';'       { $$ = $3; }
-        |       yNOT    delayE gateNotList ';'          { $$ = $3; }
-        |       yNOTIF0 delayE gateNotif0List ';'       { $$ = $3; }
-        |       yNOTIF1 delayE gateNotif1List ';'       { $$ = $3; }
-        |       yAND  delayE gateAndList ';'            { $$ = $3; }
-        |       yNAND delayE gateNandList ';'           { $$ = $3; }
-        |       yOR   delayE gateOrList ';'             { $$ = $3; }
-        |       yNOR  delayE gateNorList ';'            { $$ = $3; }
-        |       yXOR  delayE gateXorList ';'            { $$ = $3; }
-        |       yXNOR delayE gateXnorList ';'           { $$ = $3; }
-        |       yPULLUP delayE gatePullupList ';'       { $$ = $3; }
-        |       yPULLDOWN delayE gatePulldownList ';'   { $$ = $3; }
-        |       yNMOS delayE gateBufif1List ';'         { $$ = $3; }  // ~=bufif1, as don't have strengths yet
-        |       yPMOS delayE gateBufif0List ';'         { $$ = $3; }  // ~=bufif0, as don't have strengths yet
+                yBUF    delayE gateBufList ';'          { $$ = $3; PRIMDLYUNSUP($2); }
+        |       yBUFIF0 delayE gateBufif0List ';'       { $$ = $3; PRIMDLYUNSUP($2); }
+        |       yBUFIF1 delayE gateBufif1List ';'       { $$ = $3; PRIMDLYUNSUP($2); }
+        |       yNOT    delayE gateNotList ';'          { $$ = $3; PRIMDLYUNSUP($2); }
+        |       yNOTIF0 delayE gateNotif0List ';'       { $$ = $3; PRIMDLYUNSUP($2); }
+        |       yNOTIF1 delayE gateNotif1List ';'       { $$ = $3; PRIMDLYUNSUP($2); }
+        |       yAND  delayE gateAndList ';'            { $$ = $3; PRIMDLYUNSUP($2); }
+        |       yNAND delayE gateNandList ';'           { $$ = $3; PRIMDLYUNSUP($2); }
+        |       yOR   delayE gateOrList ';'             { $$ = $3; PRIMDLYUNSUP($2); }
+        |       yNOR  delayE gateNorList ';'            { $$ = $3; PRIMDLYUNSUP($2); }
+        |       yXOR  delayE gateXorList ';'            { $$ = $3; PRIMDLYUNSUP($2); }
+        |       yXNOR delayE gateXnorList ';'           { $$ = $3; PRIMDLYUNSUP($2); }
+        |       yPULLUP delayE gatePullupList ';'       { $$ = $3; PRIMDLYUNSUP($2); }
+        |       yPULLDOWN delayE gatePulldownList ';'   { $$ = $3; PRIMDLYUNSUP($2); }
+        |       yNMOS delayE gateBufif1List ';'         { $$ = $3; PRIMDLYUNSUP($2); }  // ~=bufif1, as don't have strengths yet
+        |       yPMOS delayE gateBufif0List ';'         { $$ = $3; PRIMDLYUNSUP($2); }  // ~=bufif0, as don't have strengths yet
         //
         |       yTRAN delayE gateUnsupList ';'          { $$ = $3; GATEUNSUP($3,"tran"); } // Unsupported
         |       yRCMOS delayE gateUnsupList ';'         { $$ = $3; GATEUNSUP($3,"rcmos"); } // Unsupported
diff --git a/test_regress/t/t_delay_stmtdly_bad.out b/test_regress/t/t_delay_stmtdly_bad.out
index 87c088ddc..fe957acdb 100644
--- a/test_regress/t/t_delay_stmtdly_bad.out
+++ b/test_regress/t/t_delay_stmtdly_bad.out
@@ -1,17 +1,21 @@
-%Warning-ASSIGNDLY: t/t_delay.v:22:13: Unsupported: Ignoring delay on this assignment/primitive.
+%Warning-ASSIGNDLY: t/t_delay.v:22:13: Unsupported: Ignoring timing control on this assignment.
+                                     : ... In instance t
    22 |    assign #(1.2000000000000000) dly1 = dly0 + 32'h1;
       |             ^~~~~~~~~~~~~~~~~~
                     ... For warning description see https://verilator.org/warn/ASSIGNDLY?v=latest
                     ... Use "/* verilator lint_off ASSIGNDLY */" and lint_on around source to disable this message.
-%Warning-ASSIGNDLY: t/t_delay.v:27:19: Unsupported: Ignoring delay on this assignment/primitive.
+%Warning-ASSIGNDLY: t/t_delay.v:27:19: Unsupported: Ignoring timing control on this assignment.
+                                     : ... In instance t
    27 |          dly0 <= #0 32'h11;
       |                   ^
-%Warning-ASSIGNDLY: t/t_delay.v:30:19: Unsupported: Ignoring delay on this assignment/primitive.
+%Warning-ASSIGNDLY: t/t_delay.v:30:19: Unsupported: Ignoring timing control on this assignment.
+                                     : ... In instance t
    30 |          dly0 <= #0.12 dly0 + 32'h12;
       |                   ^~~~
-%Warning-ASSIGNDLY: t/t_delay.v:38:25: Unsupported: Ignoring delay on this assignment/primitive.
+%Warning-ASSIGNDLY: t/t_delay.v:38:26: Unsupported: Ignoring timing control on this assignment.
+                                     : ... In instance t
    38 |          dly0 <= #(dly_s.dly) 32'h55;
-      |                         ^
+      |                          ^~~
 %Warning-STMTDLY: t/t_delay.v:43:11: Unsupported: Ignoring delay on this delayed statement.
                                    : ... In instance t
    43 |          #100 $finish;
diff --git a/test_regress/t/t_gate_delay_unsup.out b/test_regress/t/t_gate_delay_unsup.out
new file mode 100644
index 000000000..7a1697074
--- /dev/null
+++ b/test_regress/t/t_gate_delay_unsup.out
@@ -0,0 +1,12 @@
+%Warning-ASSIGNDLY: t/t_gate_basic.v:23:12: Unsupported: Ignoring delay on this primitive.
+   23 |    not   #(0.108) NT0 (nt0, a[0]);
+      |            ^~~~~
+                    ... For warning description see https://verilator.org/warn/ASSIGNDLY?v=latest
+                    ... Use "/* verilator lint_off ASSIGNDLY */" and lint_on around source to disable this message.
+%Warning-ASSIGNDLY: t/t_gate_basic.v:24:11: Unsupported: Ignoring delay on this primitive.
+   24 |    and   #1       AN0 (an0, a[0], b[0]);
+      |           ^
+%Warning-ASSIGNDLY: t/t_gate_basic.v:25:12: Unsupported: Ignoring delay on this primitive.
+   25 |    nand  #(2,3)   ND0 (nd0, a[0], b[0], b[1]);
+      |            ^
+%Error: Exiting due to
diff --git a/test_regress/t/t_gate_delay_unsup.pl b/test_regress/t/t_gate_delay_unsup.pl
new file mode 100755
index 000000000..2f885e5ae
--- /dev/null
+++ b/test_regress/t/t_gate_delay_unsup.pl
@@ -0,0 +1,22 @@
+#!/usr/bin/env perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2022 by Antmicro Ltd. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+scenarios(linter => 1);
+
+top_filename("t/t_gate_basic.v");
+
+lint(
+    verilator_flags2 => ["--lint-only -Wall -Wno-DECLFILENAME -Wno-UNUSED"],
+    fails => 1,
+    expect_filename => $Self->{golden_filename},
+    );
+
+ok(1);
+1;
diff --git a/test_regress/t/t_timing_intra_assign_delay.out b/test_regress/t/t_timing_intra_assign_delay.out
new file mode 100644
index 000000000..f726ad4b4
--- /dev/null
+++ b/test_regress/t/t_timing_intra_assign_delay.out
@@ -0,0 +1,31 @@
+%Warning-ASSIGNDLY: t/t_timing_intra_assign_delay.v:12:11: Unsupported: Ignoring timing control on this assignment.
+                                                         : ... In instance t
+   12 |   assign #10 val2 = val1;
+      |           ^~
+                    ... For warning description see https://verilator.org/warn/ASSIGNDLY?v=latest
+                    ... Use "/* verilator lint_off ASSIGNDLY */" and lint_on around source to disable this message.
+%Warning-STMTDLY: t/t_timing_intra_assign_delay.v:16:6: Unsupported: Ignoring delay on this delayed statement.
+                                                      : ... In instance t
+   16 |     #10 val1 = 2;
+      |      ^~
+%Error-UNSUPPORTED: t/t_timing_intra_assign_delay.v:17:5: Unsupported: fork statements
+                                                        : ... In instance t
+   17 |     fork #5 val1 = 3; join_none
+      |     ^~~~
+%Warning-ASSIGNDLY: t/t_timing_intra_assign_delay.v:18:13: Unsupported: Ignoring timing control on this assignment.
+                                                         : ... In instance t
+   18 |     val1 = #10 val1 + 2;
+      |             ^~
+%Warning-ASSIGNDLY: t/t_timing_intra_assign_delay.v:19:14: Unsupported: Ignoring timing control on this assignment.
+                                                         : ... In instance t
+   19 |     val1 <= #10 val1 + 2;
+      |              ^~
+%Error-UNSUPPORTED: t/t_timing_intra_assign_delay.v:20:5: Unsupported: fork statements
+                                                        : ... In instance t
+   20 |     fork #5 val1 = 5; join_none
+      |     ^~~~
+%Warning-STMTDLY: t/t_timing_intra_assign_delay.v:21:6: Unsupported: Ignoring delay on this delayed statement.
+                                                      : ... In instance t
+   21 |     #20 $write("*-* All Finished *-*\n");
+      |      ^~
+%Error: Exiting due to
diff --git a/test_regress/t/t_timing_intra_assign_delay.pl b/test_regress/t/t_timing_intra_assign_delay.pl
new file mode 100755
index 000000000..d61820774
--- /dev/null
+++ b/test_regress/t/t_timing_intra_assign_delay.pl
@@ -0,0 +1,20 @@
+#!/usr/bin/env perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2022 by Antmicro Ltd. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+scenarios(simulator => 1);
+
+lint(
+    verilator_flags2 => ['-Wall -Wno-DECLFILENAME'],
+    fails => 1,
+    expect_filename => $Self->{golden_filename},
+    );
+
+ok(1);
+1;
diff --git a/test_regress/t/t_timing_intra_assign_delay.v b/test_regress/t/t_timing_intra_assign_delay.v
new file mode 100644
index 000000000..4ddc2461d
--- /dev/null
+++ b/test_regress/t/t_timing_intra_assign_delay.v
@@ -0,0 +1,24 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2022 by Antmicro Ltd.
+// SPDX-License-Identifier: CC0-1.0
+
+module t;
+  int val1, val2;
+
+  always @val1 $write("[%0t] val1=%0d val2=%0d\n", $time, val1, val2);
+
+  assign #10 val2 = val1;
+
+  initial begin
+    val1 = 1;
+    #10 val1 = 2;
+    fork #5 val1 = 3; join_none
+    val1 = #10 val1 + 2;
+    val1 <= #10 val1 + 2;
+    fork #5 val1 = 5; join_none
+    #20 $write("*-* All Finished *-*\n");
+    $finish;
+  end
+endmodule
diff --git a/test_regress/t/t_timing_intra_assign_event.out b/test_regress/t/t_timing_intra_assign_event.out
new file mode 100644
index 000000000..3fd9349f3
--- /dev/null
+++ b/test_regress/t/t_timing_intra_assign_event.out
@@ -0,0 +1,32 @@
+%Error-UNSUPPORTED: t/t_timing_intra_assign_event.v:15:5: Unsupported: event control statement in this location
+                                                        : ... In instance t
+                                                        : ... Suggest have one event control statement per procedure, at the top of the procedure
+   15 |     @e val = 2;
+      |     ^
+                    ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest
+%Error-UNSUPPORTED: t/t_timing_intra_assign_event.v:16:5: Unsupported: fork statements
+                                                        : ... In instance t
+   16 |     fork begin
+      |     ^~~~
+%Warning-ASSIGNDLY: t/t_timing_intra_assign_event.v:21:11: Unsupported: Ignoring timing control on this assignment.
+                                                         : ... In instance t
+   21 |     val = @e val + 2;
+      |           ^
+                    ... Use "/* verilator lint_off ASSIGNDLY */" and lint_on around source to disable this message.
+%Warning-ASSIGNDLY: t/t_timing_intra_assign_event.v:22:12: Unsupported: Ignoring timing control on this assignment.
+                                                         : ... In instance t
+   22 |     val <= @e val + 2;
+      |            ^
+%Error-UNSUPPORTED: t/t_timing_intra_assign_event.v:23:5: Unsupported: fork statements
+                                                        : ... In instance t
+   23 |     fork begin
+      |     ^~~~
+%Warning-STMTDLY: t/t_timing_intra_assign_event.v:29:6: Unsupported: Ignoring delay on this delayed statement.
+                                                      : ... In instance t
+   29 |     #1 $write("*-* All Finished *-*\n");
+      |      ^
+%Warning-STMTDLY: t/t_timing_intra_assign_event.v:33:12: Unsupported: Ignoring delay on this delayed statement.
+                                                       : ... In instance t
+   33 |   initial #1 ->e;
+      |            ^
+%Error: Exiting due to
diff --git a/test_regress/t/t_timing_intra_assign_event.pl b/test_regress/t/t_timing_intra_assign_event.pl
new file mode 100755
index 000000000..d61820774
--- /dev/null
+++ b/test_regress/t/t_timing_intra_assign_event.pl
@@ -0,0 +1,20 @@
+#!/usr/bin/env perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2022 by Antmicro Ltd. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+scenarios(simulator => 1);
+
+lint(
+    verilator_flags2 => ['-Wall -Wno-DECLFILENAME'],
+    fails => 1,
+    expect_filename => $Self->{golden_filename},
+    );
+
+ok(1);
+1;
diff --git a/test_regress/t/t_timing_intra_assign_event.v b/test_regress/t/t_timing_intra_assign_event.v
new file mode 100644
index 000000000..d98da3a66
--- /dev/null
+++ b/test_regress/t/t_timing_intra_assign_event.v
@@ -0,0 +1,34 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2022 by Antmicro Ltd.
+// SPDX-License-Identifier: CC0-1.0
+
+module t;
+  int val;
+  event e;
+
+  always @val $write("val=%0d\n", val);
+
+  initial begin
+    val = 1;
+    @e val = 2;
+    fork begin
+        @e #1 val = 3;
+        ->e;
+    end join_none
+    ->e;
+    val = @e val + 2;
+    val <= @e val + 2;
+    fork begin
+        @e val = 5;
+        ->e;
+    end join_none
+    ->e;
+    ->e;
+    #1 $write("*-* All Finished *-*\n");
+    $finish;
+  end
+
+  initial #1 ->e;
+endmodule
diff --git a/test_regress/t/t_timing_net_delay.out b/test_regress/t/t_timing_net_delay.out
new file mode 100644
index 000000000..116ccc0a0
--- /dev/null
+++ b/test_regress/t/t_timing_net_delay.out
@@ -0,0 +1,11 @@
+%Warning-ASSIGNDLY: t/t_timing_net_delay.v:13:15: Unsupported: Ignoring timing control on this assignment.
+                                                : ... In instance t
+   13 |    wire[3:0] #4 val1 = cyc;
+      |               ^
+                    ... For warning description see https://verilator.org/warn/ASSIGNDLY?v=latest
+                    ... Use "/* verilator lint_off ASSIGNDLY */" and lint_on around source to disable this message.
+%Warning-ASSIGNDLY: t/t_timing_net_delay.v:17:12: Unsupported: Ignoring timing control on this assignment.
+                                                : ... In instance t
+   17 |    assign #4 val2 = cyc;
+      |            ^
+%Error: Exiting due to
diff --git a/test_regress/t/t_timing_net_delay.pl b/test_regress/t/t_timing_net_delay.pl
new file mode 100755
index 000000000..d61820774
--- /dev/null
+++ b/test_regress/t/t_timing_net_delay.pl
@@ -0,0 +1,20 @@
+#!/usr/bin/env perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2022 by Antmicro Ltd. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+scenarios(simulator => 1);
+
+lint(
+    verilator_flags2 => ['-Wall -Wno-DECLFILENAME'],
+    fails => 1,
+    expect_filename => $Self->{golden_filename},
+    );
+
+ok(1);
+1;
diff --git a/test_regress/t/t_timing_net_delay.v b/test_regress/t/t_timing_net_delay.v
new file mode 100644
index 000000000..aa125ca8c
--- /dev/null
+++ b/test_regress/t/t_timing_net_delay.v
@@ -0,0 +1,30 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2022 by Antmicro Ltd.
+// SPDX-License-Identifier: CC0-1.0
+
+module t (/*AUTOARG*/
+   // Inputs
+   clk
+   );
+   input clk;
+
+   wire[3:0] #4 val1 = cyc;
+   wire[3:0] #4 val2;
+   reg[3:0] cyc = 0;
+
+   assign #4 val2 = cyc;
+
+   always @(posedge clk) begin
+       cyc <= cyc + 1;
+`ifdef TEST_VERBOSE
+       $write("[%0t] cyc=%0d, val1=%0d, val2=%0d\n", $time, cyc, val1, val2);
+`endif
+       if (cyc >= 4 && val1 != cyc-1 && val2 != cyc-3) $stop;
+       if (cyc == 15) begin
+           $write("*-* All Finished *-*\n");
+           $finish;
+       end
+   end
+endmodule

From 551bd284dd16097d006bea90124bb47f626b9ea3 Mon Sep 17 00:00:00 2001
From: Geza Lore <gezalore@gmail.com>
Date: Fri, 20 May 2022 15:28:25 +0100
Subject: [PATCH 17/23] Rename some internals related to multi-threaded tracing

Rename the implementation internals of current multi-threaded tracing to
be "offload mode". No functional change, nor user interface change
intended.
---
 include/verilated_trace.h       | 124 +++++++++++++-------------
 include/verilated_trace_imp.cpp | 153 ++++++++++++++++----------------
 include/verilated_vcd_c.cpp     |   2 +-
 src/V3EmitCImp.cpp              |   2 +-
 src/V3EmitMk.cpp                |   2 +-
 src/V3Options.h                 |   2 +-
 src/V3Trace.cpp                 |   2 +-
 7 files changed, 146 insertions(+), 141 deletions(-)

diff --git a/include/verilated_trace.h b/include/verilated_trace.h
index de000e611..a88ce6b50 100644
--- a/include/verilated_trace.h
+++ b/include/verilated_trace.h
@@ -22,6 +22,10 @@
 #ifndef VERILATOR_VERILATED_TRACE_H_
 #define VERILATOR_VERILATED_TRACE_H_
 
+#ifdef VL_TRACE_THREADED
+#define VL_TRACE_OFFLOAD
+#endif
+
 // clang-format off
 
 #include "verilated.h"
@@ -32,7 +36,7 @@
 #include <string>
 #include <vector>
 
-#ifdef VL_TRACE_THREADED
+#ifdef VL_TRACE_OFFLOAD
 # include <condition_variable>
 # include <deque>
 # include <thread>
@@ -40,9 +44,9 @@
 
 // clang-format on
 
-#ifdef VL_TRACE_THREADED
+#ifdef VL_TRACE_OFFLOAD
 //=============================================================================
-// Threaded tracing
+// Offloaded tracing
 
 // A simple synchronized first in first out queue
 template <class T> class VerilatedThreadQueue final {  // LCOV_EXCL_LINE  // lcov bug
@@ -88,7 +92,7 @@ public:
 
 // Commands used by thread tracing. Anonymous enum in class, as we want
 // it scoped, but we also want the automatic conversion to integer types.
-class VerilatedTraceCommand final {
+class VerilatedTraceOffloadCommand final {
 public:
     // These must all fit in 4 bit at the moment, as the tracing routines
     // pack parameters in the top bits.
@@ -172,33 +176,33 @@ private:
     // Close the file on termination
     static void onExit(void* selfp) VL_MT_UNSAFE_ONE;
 
-#ifdef VL_TRACE_THREADED
-    // Number of total trace buffers that have been allocated
-    uint32_t m_numTraceBuffers;
-    // Size of trace buffers
-    size_t m_traceBufferSize;
+#ifdef VL_TRACE_OFFLOAD
+    // Number of total offload buffers that have been allocated
+    uint32_t m_numOffloadBuffers;
+    // Size of offload buffers
+    size_t m_offloadBufferSize;
     // Buffers handed to worker for processing
-    VerilatedThreadQueue<uint32_t*> m_buffersToWorker;
+    VerilatedThreadQueue<uint32_t*> m_offloadBuffersToWorker;
     // Buffers returned from worker after processing
-    VerilatedThreadQueue<uint32_t*> m_buffersFromWorker;
+    VerilatedThreadQueue<uint32_t*> m_offloadBuffersFromWorker;
     // Write pointer into current buffer
-    uint32_t* m_traceBufferWritep;
-    // End of trace buffer
-    uint32_t* m_traceBufferEndp;
-    // The worker thread itself
+    uint32_t* m_offloadBufferWritep;
+    // End of offload buffer
+    uint32_t* m_offloadBufferEndp;
+    // The offload worker thread itself
     std::unique_ptr<std::thread> m_workerThread;
 
-    // Get a new trace buffer that can be populated. May block if none available
-    uint32_t* getTraceBuffer();
+    // Get a new offload buffer that can be populated. May block if none available
+    uint32_t* getOffloadBuffer();
 
-    // The function executed by the worker thread
-    void workerThreadMain();
+    // The function executed by the offload worker thread
+    void offloadWorkerThreadMain();
 
-    // Wait until given buffer is placed in m_buffersFromWorker
-    void waitForBuffer(const uint32_t* bufferp);
+    // Wait until given offload buffer is placed in m_offloadBuffersFromWorker
+    void waitForOffloadBuffer(const uint32_t* bufferp);
 
     // Shut down and join worker, if it's running, otherwise do nothing
-    void shutdownWorker();
+    void shutdownOffloadWorker();
 #endif
 
     // CONSTRUCTORS
@@ -307,56 +311,56 @@ public:
     void fullWData(uint32_t* oldp, const WData* newvalp, int bits);
     void fullDouble(uint32_t* oldp, double newval);
 
-#ifdef VL_TRACE_THREADED
-    // Threaded tracing. Just dump everything in the trace buffer
+#ifdef VL_TRACE_OFFLOAD
+    // Offloaded tracing. Just dump everything in the offload buffer
     inline void chgBit(uint32_t code, CData newval) {
-        m_traceBufferWritep[0] = VerilatedTraceCommand::CHG_BIT_0 | newval;
-        m_traceBufferWritep[1] = code;
-        m_traceBufferWritep += 2;
-        VL_DEBUG_IF(assert(m_traceBufferWritep <= m_traceBufferEndp););
+        m_offloadBufferWritep[0] = VerilatedTraceOffloadCommand::CHG_BIT_0 | newval;
+        m_offloadBufferWritep[1] = code;
+        m_offloadBufferWritep += 2;
+        VL_DEBUG_IF(assert(m_offloadBufferWritep <= m_offloadBufferEndp););
     }
     inline void chgCData(uint32_t code, CData newval, int bits) {
-        m_traceBufferWritep[0] = (bits << 4) | VerilatedTraceCommand::CHG_CDATA;
-        m_traceBufferWritep[1] = code;
-        m_traceBufferWritep[2] = newval;
-        m_traceBufferWritep += 3;
-        VL_DEBUG_IF(assert(m_traceBufferWritep <= m_traceBufferEndp););
+        m_offloadBufferWritep[0] = (bits << 4) | VerilatedTraceOffloadCommand::CHG_CDATA;
+        m_offloadBufferWritep[1] = code;
+        m_offloadBufferWritep[2] = newval;
+        m_offloadBufferWritep += 3;
+        VL_DEBUG_IF(assert(m_offloadBufferWritep <= m_offloadBufferEndp););
     }
     inline void chgSData(uint32_t code, SData newval, int bits) {
-        m_traceBufferWritep[0] = (bits << 4) | VerilatedTraceCommand::CHG_SDATA;
-        m_traceBufferWritep[1] = code;
-        m_traceBufferWritep[2] = newval;
-        m_traceBufferWritep += 3;
-        VL_DEBUG_IF(assert(m_traceBufferWritep <= m_traceBufferEndp););
+        m_offloadBufferWritep[0] = (bits << 4) | VerilatedTraceOffloadCommand::CHG_SDATA;
+        m_offloadBufferWritep[1] = code;
+        m_offloadBufferWritep[2] = newval;
+        m_offloadBufferWritep += 3;
+        VL_DEBUG_IF(assert(m_offloadBufferWritep <= m_offloadBufferEndp););
     }
     inline void chgIData(uint32_t code, IData newval, int bits) {
-        m_traceBufferWritep[0] = (bits << 4) | VerilatedTraceCommand::CHG_IDATA;
-        m_traceBufferWritep[1] = code;
-        m_traceBufferWritep[2] = newval;
-        m_traceBufferWritep += 3;
-        VL_DEBUG_IF(assert(m_traceBufferWritep <= m_traceBufferEndp););
+        m_offloadBufferWritep[0] = (bits << 4) | VerilatedTraceOffloadCommand::CHG_IDATA;
+        m_offloadBufferWritep[1] = code;
+        m_offloadBufferWritep[2] = newval;
+        m_offloadBufferWritep += 3;
+        VL_DEBUG_IF(assert(m_offloadBufferWritep <= m_offloadBufferEndp););
     }
     inline void chgQData(uint32_t code, QData newval, int bits) {
-        m_traceBufferWritep[0] = (bits << 4) | VerilatedTraceCommand::CHG_QDATA;
-        m_traceBufferWritep[1] = code;
-        *reinterpret_cast<QData*>(m_traceBufferWritep + 2) = newval;
-        m_traceBufferWritep += 4;
-        VL_DEBUG_IF(assert(m_traceBufferWritep <= m_traceBufferEndp););
+        m_offloadBufferWritep[0] = (bits << 4) | VerilatedTraceOffloadCommand::CHG_QDATA;
+        m_offloadBufferWritep[1] = code;
+        *reinterpret_cast<QData*>(m_offloadBufferWritep + 2) = newval;
+        m_offloadBufferWritep += 4;
+        VL_DEBUG_IF(assert(m_offloadBufferWritep <= m_offloadBufferEndp););
     }
     inline void chgWData(uint32_t code, const WData* newvalp, int bits) {
-        m_traceBufferWritep[0] = (bits << 4) | VerilatedTraceCommand::CHG_WDATA;
-        m_traceBufferWritep[1] = code;
-        m_traceBufferWritep += 2;
-        for (int i = 0; i < (bits + 31) / 32; ++i) { *m_traceBufferWritep++ = newvalp[i]; }
-        VL_DEBUG_IF(assert(m_traceBufferWritep <= m_traceBufferEndp););
+        m_offloadBufferWritep[0] = (bits << 4) | VerilatedTraceOffloadCommand::CHG_WDATA;
+        m_offloadBufferWritep[1] = code;
+        m_offloadBufferWritep += 2;
+        for (int i = 0; i < (bits + 31) / 32; ++i) { *m_offloadBufferWritep++ = newvalp[i]; }
+        VL_DEBUG_IF(assert(m_offloadBufferWritep <= m_offloadBufferEndp););
     }
     inline void chgDouble(uint32_t code, double newval) {
-        m_traceBufferWritep[0] = VerilatedTraceCommand::CHG_DOUBLE;
-        m_traceBufferWritep[1] = code;
+        m_offloadBufferWritep[0] = VerilatedTraceOffloadCommand::CHG_DOUBLE;
+        m_offloadBufferWritep[1] = code;
         // cppcheck-suppress invalidPointerCast
-        *reinterpret_cast<double*>(m_traceBufferWritep + 2) = newval;
-        m_traceBufferWritep += 4;
-        VL_DEBUG_IF(assert(m_traceBufferWritep <= m_traceBufferEndp););
+        *reinterpret_cast<double*>(m_offloadBufferWritep + 2) = newval;
+        m_offloadBufferWritep += 4;
+        VL_DEBUG_IF(assert(m_offloadBufferWritep <= m_offloadBufferEndp););
     }
 
 #define CHG(name) chg##name##Impl
@@ -364,8 +368,8 @@ public:
 #define CHG(name) chg##name
 #endif
 
-    // In non-threaded mode, these are called directly by the trace callbacks,
-    // and are called chg*. In threaded mode, they are called by the worker
+    // In non-offload mode, these are called directly by the trace callbacks,
+    // and are called chg*. In offload mode, they are called by the worker
     // thread and are called chg*Impl
 
     // Check previous dumped value of signal. If changed, then emit trace entry
diff --git a/include/verilated_trace_imp.cpp b/include/verilated_trace_imp.cpp
index e5dd41fcd..7a98b7abf 100644
--- a/include/verilated_trace_imp.cpp
+++ b/include/verilated_trace_imp.cpp
@@ -33,9 +33,9 @@
 
 #if 0
 # include <iostream>
-# define VL_TRACE_THREAD_DEBUG(msg) std::cout << "TRACE THREAD: " << msg << std::endl
+# define VL_TRACE_OFFLOAD_DEBUG(msg) std::cout << "TRACE OFFLOAD THREAD: " << msg << std::endl
 #else
-# define VL_TRACE_THREAD_DEBUG(msg)
+# define VL_TRACE_OFFLOAD_DEBUG(msg)
 #endif
 
 // clang-format on
@@ -78,37 +78,37 @@ static std::string doubleToTimescale(double value) {
     return valuestr;  // Gets converted to string, so no ref to stack
 }
 
-#ifdef VL_TRACE_THREADED
+#ifdef VL_TRACE_OFFLOAD
 //=========================================================================
 // Buffer management
 
-template <> uint32_t* VerilatedTrace<VL_DERIVED_T>::getTraceBuffer() {
+template <> uint32_t* VerilatedTrace<VL_DERIVED_T>::getOffloadBuffer() {
     uint32_t* bufferp;
-    // Some jitter is expected, so some number of alternative trace buffers are
+    // Some jitter is expected, so some number of alternative offlaod buffers are
     // required, but don't allocate more than 8 buffers.
-    if (m_numTraceBuffers < 8) {
+    if (m_numOffloadBuffers < 8) {
         // Allocate a new buffer if none is available
-        if (!m_buffersFromWorker.tryGet(bufferp)) {
-            ++m_numTraceBuffers;
+        if (!m_offloadBuffersFromWorker.tryGet(bufferp)) {
+            ++m_numOffloadBuffers;
             // Note: over allocate a bit so pointer comparison is well defined
             // if we overflow only by a small amount
-            bufferp = new uint32_t[m_traceBufferSize + 16];
+            bufferp = new uint32_t[m_offloadBufferSize + 16];
         }
     } else {
         // Block until a buffer becomes available
-        bufferp = m_buffersFromWorker.get();
+        bufferp = m_offloadBuffersFromWorker.get();
     }
     return bufferp;
 }
 
-template <> void VerilatedTrace<VL_DERIVED_T>::waitForBuffer(const uint32_t* buffp) {
+template <> void VerilatedTrace<VL_DERIVED_T>::waitForOffloadBuffer(const uint32_t* buffp) {
     // Slow path code only called on flush/shutdown, so use a simple algorithm.
     // Collect buffers from worker and stash them until we get the one we want.
     std::deque<uint32_t*> stash;
-    do { stash.push_back(m_buffersFromWorker.get()); } while (stash.back() != buffp);
+    do { stash.push_back(m_offloadBuffersFromWorker.get()); } while (stash.back() != buffp);
     // Now put them back in the queue, in the original order.
     while (!stash.empty()) {
-        m_buffersFromWorker.put_front(stash.back());
+        m_offloadBuffersFromWorker.put_front(stash.back());
         stash.pop_back();
     }
 }
@@ -116,14 +116,14 @@ template <> void VerilatedTrace<VL_DERIVED_T>::waitForBuffer(const uint32_t* buf
 //=========================================================================
 // Worker thread
 
-template <> void VerilatedTrace<VL_DERIVED_T>::workerThreadMain() {
+template <> void VerilatedTrace<VL_DERIVED_T>::offloadWorkerThreadMain() {
     bool shutdown = false;
 
     do {
-        uint32_t* const bufferp = m_buffersToWorker.get();
+        uint32_t* const bufferp = m_offloadBuffersToWorker.get();
 
-        VL_TRACE_THREAD_DEBUG("");
-        VL_TRACE_THREAD_DEBUG("Got buffer: " << bufferp);
+        VL_TRACE_OFFLOAD_DEBUG("");
+        VL_TRACE_OFFLOAD_DEBUG("Got buffer: " << bufferp);
 
         const uint32_t* readp = bufferp;
 
@@ -139,53 +139,53 @@ template <> void VerilatedTrace<VL_DERIVED_T>::workerThreadMain() {
             switch (cmd & 0xF) {
                 //===
                 // CHG_* commands
-            case VerilatedTraceCommand::CHG_BIT_0:
-                VL_TRACE_THREAD_DEBUG("Command CHG_BIT_0 " << top);
+            case VerilatedTraceOffloadCommand::CHG_BIT_0:
+                VL_TRACE_OFFLOAD_DEBUG("Command CHG_BIT_0 " << top);
                 chgBitImpl(oldp, 0);
                 continue;
-            case VerilatedTraceCommand::CHG_BIT_1:
-                VL_TRACE_THREAD_DEBUG("Command CHG_BIT_1 " << top);
+            case VerilatedTraceOffloadCommand::CHG_BIT_1:
+                VL_TRACE_OFFLOAD_DEBUG("Command CHG_BIT_1 " << top);
                 chgBitImpl(oldp, 1);
                 continue;
-            case VerilatedTraceCommand::CHG_CDATA:
-                VL_TRACE_THREAD_DEBUG("Command CHG_CDATA " << top);
+            case VerilatedTraceOffloadCommand::CHG_CDATA:
+                VL_TRACE_OFFLOAD_DEBUG("Command CHG_CDATA " << top);
                 // Bits stored in bottom byte of command
                 chgCDataImpl(oldp, *readp, top);
                 readp += 1;
                 continue;
-            case VerilatedTraceCommand::CHG_SDATA:
-                VL_TRACE_THREAD_DEBUG("Command CHG_SDATA " << top);
+            case VerilatedTraceOffloadCommand::CHG_SDATA:
+                VL_TRACE_OFFLOAD_DEBUG("Command CHG_SDATA " << top);
                 // Bits stored in bottom byte of command
                 chgSDataImpl(oldp, *readp, top);
                 readp += 1;
                 continue;
-            case VerilatedTraceCommand::CHG_IDATA:
-                VL_TRACE_THREAD_DEBUG("Command CHG_IDATA " << top);
+            case VerilatedTraceOffloadCommand::CHG_IDATA:
+                VL_TRACE_OFFLOAD_DEBUG("Command CHG_IDATA " << top);
                 // Bits stored in bottom byte of command
                 chgIDataImpl(oldp, *readp, top);
                 readp += 1;
                 continue;
-            case VerilatedTraceCommand::CHG_QDATA:
-                VL_TRACE_THREAD_DEBUG("Command CHG_QDATA " << top);
+            case VerilatedTraceOffloadCommand::CHG_QDATA:
+                VL_TRACE_OFFLOAD_DEBUG("Command CHG_QDATA " << top);
                 // Bits stored in bottom byte of command
                 chgQDataImpl(oldp, *reinterpret_cast<const QData*>(readp), top);
                 readp += 2;
                 continue;
-            case VerilatedTraceCommand::CHG_WDATA:
-                VL_TRACE_THREAD_DEBUG("Command CHG_WDATA " << top);
+            case VerilatedTraceOffloadCommand::CHG_WDATA:
+                VL_TRACE_OFFLOAD_DEBUG("Command CHG_WDATA " << top);
                 chgWDataImpl(oldp, readp, top);
                 readp += VL_WORDS_I(top);
                 continue;
-            case VerilatedTraceCommand::CHG_DOUBLE:
-                VL_TRACE_THREAD_DEBUG("Command CHG_DOUBLE " << top);
+            case VerilatedTraceOffloadCommand::CHG_DOUBLE:
+                VL_TRACE_OFFLOAD_DEBUG("Command CHG_DOUBLE " << top);
                 chgDoubleImpl(oldp, *reinterpret_cast<const double*>(readp));
                 readp += 2;
                 continue;
 
                 //===
                 // Rare commands
-            case VerilatedTraceCommand::TIME_CHANGE:
-                VL_TRACE_THREAD_DEBUG("Command TIME_CHANGE " << top);
+            case VerilatedTraceOffloadCommand::TIME_CHANGE:
+                VL_TRACE_OFFLOAD_DEBUG("Command TIME_CHANGE " << top);
                 readp -= 1;  // No code in this command, undo increment
                 emitTimeChange(*reinterpret_cast<const uint64_t*>(readp));
                 readp += 2;
@@ -193,16 +193,16 @@ template <> void VerilatedTrace<VL_DERIVED_T>::workerThreadMain() {
 
                 //===
                 // Commands ending this buffer
-            case VerilatedTraceCommand::END: VL_TRACE_THREAD_DEBUG("Command END"); break;
-            case VerilatedTraceCommand::SHUTDOWN:
-                VL_TRACE_THREAD_DEBUG("Command SHUTDOWN");
+            case VerilatedTraceOffloadCommand::END: VL_TRACE_OFFLOAD_DEBUG("Command END"); break;
+            case VerilatedTraceOffloadCommand::SHUTDOWN:
+                VL_TRACE_OFFLOAD_DEBUG("Command SHUTDOWN");
                 shutdown = true;
                 break;
 
             //===
             // Unknown command
             default: {  // LCOV_EXCL_START
-                VL_TRACE_THREAD_DEBUG("Command UNKNOWN");
+                VL_TRACE_OFFLOAD_DEBUG("Command UNKNOWN");
                 VL_PRINTF_MT("Trace command: 0x%08x\n", cmd);
                 VL_FATAL_MT(__FILE__, __LINE__, "", "Unknown trace command");
                 break;
@@ -214,23 +214,23 @@ template <> void VerilatedTrace<VL_DERIVED_T>::workerThreadMain() {
             break;
         }
 
-        VL_TRACE_THREAD_DEBUG("Returning buffer");
+        VL_TRACE_OFFLOAD_DEBUG("Returning buffer");
 
         // Return buffer
-        m_buffersFromWorker.put(bufferp);
+        m_offloadBuffersFromWorker.put(bufferp);
     } while (VL_LIKELY(!shutdown));
 }
 
-template <> void VerilatedTrace<VL_DERIVED_T>::shutdownWorker() {
+template <> void VerilatedTrace<VL_DERIVED_T>::shutdownOffloadWorker() {
     // If the worker thread is not running, done..
     if (!m_workerThread) return;
 
     // Hand an buffer with a shutdown command to the worker thread
-    uint32_t* const bufferp = getTraceBuffer();
-    bufferp[0] = VerilatedTraceCommand::SHUTDOWN;
-    m_buffersToWorker.put(bufferp);
+    uint32_t* const bufferp = getOffloadBuffer();
+    bufferp[0] = VerilatedTraceOffloadCommand::SHUTDOWN;
+    m_offloadBuffersToWorker.put(bufferp);
     // Wait for it to return
-    waitForBuffer(bufferp);
+    waitForOffloadBuffer(bufferp);
     // Join the thread and delete it
     m_workerThread->join();
     m_workerThread.reset(nullptr);
@@ -242,24 +242,24 @@ template <> void VerilatedTrace<VL_DERIVED_T>::shutdownWorker() {
 // Life cycle
 
 template <> void VerilatedTrace<VL_DERIVED_T>::closeBase() {
-#ifdef VL_TRACE_THREADED
-    shutdownWorker();
-    while (m_numTraceBuffers) {
-        delete[] m_buffersFromWorker.get();
-        --m_numTraceBuffers;
+#ifdef VL_TRACE_OFFLOAD
+    shutdownOffloadWorker();
+    while (m_numOffloadBuffers) {
+        delete[] m_offloadBuffersFromWorker.get();
+        --m_numOffloadBuffers;
     }
 #endif
 }
 
 template <> void VerilatedTrace<VL_DERIVED_T>::flushBase() {
-#ifdef VL_TRACE_THREADED
+#ifdef VL_TRACE_OFFLOAD
     // Hand an empty buffer to the worker thread
-    uint32_t* const bufferp = getTraceBuffer();
-    *bufferp = VerilatedTraceCommand::END;
-    m_buffersToWorker.put(bufferp);
+    uint32_t* const bufferp = getOffloadBuffer();
+    *bufferp = VerilatedTraceOffloadCommand::END;
+    m_offloadBuffersToWorker.put(bufferp);
     // Wait for it to be returned. As the processing is in-order,
     // this ensures all previous buffers have been processed.
-    waitForBuffer(bufferp);
+    waitForOffloadBuffer(bufferp);
 #endif
 }
 
@@ -293,8 +293,8 @@ VerilatedTrace<VL_DERIVED_T>::VerilatedTrace()
     , m_timeUnit {
     1e-9
 }
-#ifdef VL_TRACE_THREADED
-, m_numTraceBuffers { 0 }
+#ifdef VL_TRACE_OFFLOAD
+, m_numOffloadBuffers { 0 }
 #endif
 {
     set_time_unit(Verilated::threadContextp()->timeunitString());
@@ -306,7 +306,7 @@ template <> VerilatedTrace<VL_DERIVED_T>::~VerilatedTrace() {
     if (m_sigs_enabledp) VL_DO_CLEAR(delete[] m_sigs_enabledp, m_sigs_enabledp = nullptr);
     Verilated::removeFlushCb(VerilatedTrace<VL_DERIVED_T>::onFlush, this);
     Verilated::removeExitCb(VerilatedTrace<VL_DERIVED_T>::onExit, this);
-#ifdef VL_TRACE_THREADED
+#ifdef VL_TRACE_OFFLOAD
     closeBase();
 #endif
 }
@@ -362,16 +362,17 @@ template <> void VerilatedTrace<VL_DERIVED_T>::traceInit() VL_MT_UNSAFE {
     Verilated::addFlushCb(VerilatedTrace<VL_DERIVED_T>::onFlush, this);
     Verilated::addExitCb(VerilatedTrace<VL_DERIVED_T>::onExit, this);
 
-#ifdef VL_TRACE_THREADED
-    // Compute trace buffer size. we need to be able to store a new value for
+#ifdef VL_TRACE_OFFLOAD
+    // Compute offload buffer size. we need to be able to store a new value for
     // each signal, which is 'nextCode()' entries after the init callbacks
     // above have been run, plus up to 2 more words of metadata per signal,
     // plus fixed overhead of 1 for a termination flag and 3 for a time stamp
     // update.
-    m_traceBufferSize = nextCode() + numSignals() * 2 + 4;
+    m_offloadBufferSize = nextCode() + numSignals() * 2 + 4;
 
     // Start the worker thread
-    m_workerThread.reset(new std::thread{&VerilatedTrace<VL_DERIVED_T>::workerThreadMain, this});
+    m_workerThread.reset(
+        new std::thread{&VerilatedTrace<VL_DERIVED_T>::offloadWorkerThreadMain, this});
 #endif
 }
 
@@ -477,19 +478,19 @@ template <> void VerilatedTrace<VL_DERIVED_T>::dump(uint64_t timeui) VL_MT_SAFE_
         if (!preChangeDump()) return;
     }
 
-#ifdef VL_TRACE_THREADED
+#ifdef VL_TRACE_OFFLOAD
     // Currently only incremental dumps run on the worker thread
     uint32_t* bufferp = nullptr;
     if (VL_LIKELY(!m_fullDump)) {
-        // Get the trace buffer we are about to fill
-        bufferp = getTraceBuffer();
-        m_traceBufferWritep = bufferp;
-        m_traceBufferEndp = bufferp + m_traceBufferSize;
+        // Get the offload buffer we are about to fill
+        bufferp = getOffloadBuffer();
+        m_offloadBufferWritep = bufferp;
+        m_offloadBufferEndp = bufferp + m_offloadBufferSize;
 
         // Tell worker to update time point
-        m_traceBufferWritep[0] = VerilatedTraceCommand::TIME_CHANGE;
-        *reinterpret_cast<uint64_t*>(m_traceBufferWritep + 1) = timeui;
-        m_traceBufferWritep += 3;
+        m_offloadBufferWritep[0] = VerilatedTraceOffloadCommand::TIME_CHANGE;
+        *reinterpret_cast<uint64_t*>(m_offloadBufferWritep + 1) = timeui;
+        m_offloadBufferWritep += 3;
     } else {
         // Update time point
         flushBase();
@@ -519,16 +520,16 @@ template <> void VerilatedTrace<VL_DERIVED_T>::dump(uint64_t timeui) VL_MT_SAFE_
         cbr.m_dumpCb(cbr.m_userp, self());
     }
 
-#ifdef VL_TRACE_THREADED
+#ifdef VL_TRACE_OFFLOAD
     if (VL_LIKELY(bufferp)) {
-        // Mark end of the trace buffer we just filled
-        *m_traceBufferWritep++ = VerilatedTraceCommand::END;
+        // Mark end of the offload buffer we just filled
+        *m_offloadBufferWritep++ = VerilatedTraceOffloadCommand::END;
 
         // Assert no buffer overflow
-        assert(m_traceBufferWritep - bufferp <= m_traceBufferSize);
+        assert(m_offloadBufferWritep - bufferp <= m_offloadBufferSize);
 
         // Pass it to the worker thread
-        m_buffersToWorker.put(bufferp);
+        m_offloadBuffersToWorker.put(bufferp);
     }
 #endif
 }
diff --git a/include/verilated_vcd_c.cpp b/include/verilated_vcd_c.cpp
index 855f51634..78383befc 100644
--- a/include/verilated_vcd_c.cpp
+++ b/include/verilated_vcd_c.cpp
@@ -292,7 +292,7 @@ void VerilatedVcd::bufferResize(uint64_t minsize) {
 }
 
 void VerilatedVcd::bufferFlush() VL_MT_UNSAFE_ONE {
-    // This function can be called from the trace thread
+    // This function can be called from the trace offload thread
     // This function is on the flush() call path
     // We add output data to m_writep.
     // When it gets nearly full we dump it using this routine which calls write()
diff --git a/src/V3EmitCImp.cpp b/src/V3EmitCImp.cpp
index f5da29d61..0d979b143 100644
--- a/src/V3EmitCImp.cpp
+++ b/src/V3EmitCImp.cpp
@@ -770,7 +770,7 @@ class EmitCTrace final : EmitCFunc {
 
         const uint32_t offset = (arrayindex < 0) ? 0 : (arrayindex * nodep->declp()->widthWords());
         const uint32_t code = nodep->declp()->code() + offset;
-        puts(v3Global.opt.trueTraceThreads() && !nodep->full() ? "(base+" : "(oldp+");
+        puts(v3Global.opt.useTraceOffloadThread() && !nodep->full() ? "(base+" : "(oldp+");
         puts(cvtToStr(code - nodep->baseCode()));
         puts(",");
         emitTraceValue(nodep, arrayindex);
diff --git a/src/V3EmitMk.cpp b/src/V3EmitMk.cpp
index ce75cb136..52aec9a54 100644
--- a/src/V3EmitMk.cpp
+++ b/src/V3EmitMk.cpp
@@ -71,7 +71,7 @@ public:
         of.puts("\n");
         of.puts("# Tracing threaded output mode?  0/1/N threads (from --trace-thread)\n");
         of.puts("VM_TRACE_THREADS = ");
-        of.puts(cvtToStr(v3Global.opt.trueTraceThreads()));
+        of.puts(cvtToStr(v3Global.opt.useTraceOffloadThread()));
         of.puts("\n");
         of.puts("# Separate FST writer thread? 0/1 (from --trace-fst with --trace-thread > 0)\n");
         of.puts("VM_TRACE_FST_WRITER_THREAD = ");
diff --git a/src/V3Options.h b/src/V3Options.h
index f9cf8f5d5..8c185d4ea 100644
--- a/src/V3Options.h
+++ b/src/V3Options.h
@@ -517,7 +517,7 @@ public:
     int traceMaxArray() const { return m_traceMaxArray; }
     int traceMaxWidth() const { return m_traceMaxWidth; }
     int traceThreads() const { return m_traceThreads; }
-    bool trueTraceThreads() const {
+    bool useTraceOffloadThread() const {
         return traceThreads() == 0 ? 0 : traceThreads() - traceFormat().fst();
     }
     int unrollCount() const { return m_unrollCount; }
diff --git a/src/V3Trace.cpp b/src/V3Trace.cpp
index cffd498f4..61d009b6f 100644
--- a/src/V3Trace.cpp
+++ b/src/V3Trace.cpp
@@ -520,7 +520,7 @@ private:
                            "tracep->oldp(vlSymsp->__Vm_baseCode);\n");
             } else {
                 // Change dump sub function
-                if (v3Global.opt.trueTraceThreads()) {
+                if (v3Global.opt.useTraceOffloadThread()) {
                     addInitStr("const uint32_t base VL_ATTR_UNUSED = "
                                "vlSymsp->__Vm_baseCode + "
                                + cvtToStr(baseCode) + ";\n");

From b130a8cfebd08cabbfe589e756019c688f49d85c Mon Sep 17 00:00:00 2001
From: Geza Lore <gezalore@gmail.com>
Date: Fri, 20 May 2022 16:02:43 +0100
Subject: [PATCH 18/23] Add -DVM_TRACE_VCD in model builds with Make with
 --trace

---
 Changes                 |  1 +
 include/verilated.mk.in |  1 +
 src/V3EmitCMake.cpp     | 10 +++-------
 src/V3EmitMk.cpp        |  4 ++++
 src/V3Options.h         |  1 +
 5 files changed, 10 insertions(+), 7 deletions(-)

diff --git a/Changes b/Changes
index 5c4e6c01b..7473530d0 100644
--- a/Changes
+++ b/Changes
@@ -15,6 +15,7 @@ Verilator 4.223 devel
 
 * Support compile time trace signal selection with tracing_on/off (#3323). [Shunyao CAD]
 * Add assert when VerilatedContext is mis-deleted (#3121). [Rupert Swarbrick]
+* Define VM_TRACE_VCD when tracing in VCD format. [Geza Lore, Shunyao CAD]
 * Fix hang with large case statement optimization (#3405). [Mike Urbach]
 * Fix 'with' operator with type casting (#3387). [xiak95]
 
diff --git a/include/verilated.mk.in b/include/verilated.mk.in
index 4e32df566..34e975bcc 100644
--- a/include/verilated.mk.in
+++ b/include/verilated.mk.in
@@ -56,6 +56,7 @@ VK_CPPFLAGS_ALWAYS += \
 		-DVM_SC=$(VM_SC) \
 		-DVM_TRACE=$(VM_TRACE) \
 		-DVM_TRACE_FST=$(VM_TRACE_FST) \
+		-DVM_TRACE_VCD=$(VM_TRACE_VCD) \
 		$(CFG_CXXFLAGS_NO_UNUSED) \
 
 ifeq ($(CFG_WITH_CCWARN),yes)	# Local... Else don't burden users
diff --git a/src/V3EmitCMake.cpp b/src/V3EmitCMake.cpp
index 926228c83..26f42e803 100644
--- a/src/V3EmitCMake.cpp
+++ b/src/V3EmitCMake.cpp
@@ -119,14 +119,10 @@ class CMakeEmitter final {
         cmake_set_raw(*of, name + "_TRACE_STRUCTS", cvtToStr(v3Global.opt.traceStructs()));
         *of << "# VCD Tracing output mode?  0/1 (from --trace)\n";
         cmake_set_raw(*of, name + "_TRACE_VCD",
-                      (v3Global.opt.trace() && (v3Global.opt.traceFormat() == TraceFormat::VCD))
-                          ? "1"
-                          : "0");
-        *of << "# FST Tracing output mode? 0/1 (from --fst-trace)\n";
+                      (v3Global.opt.trace() && v3Global.opt.traceFormat().vcd()) ? "1" : "0");
+        *of << "# FST Tracing output mode? 0/1 (from --trace-fst)\n";
         cmake_set_raw(*of, name + "_TRACE_FST",
-                      (v3Global.opt.trace() && (v3Global.opt.traceFormat() != TraceFormat::VCD))
-                          ? "1"
-                          : "0");
+                      (v3Global.opt.trace() && v3Global.opt.traceFormat().fst()) ? "1" : "0");
 
         *of << "\n### Sources...\n";
         std::vector<string> classes_fast;
diff --git a/src/V3EmitMk.cpp b/src/V3EmitMk.cpp
index 52aec9a54..429b78d33 100644
--- a/src/V3EmitMk.cpp
+++ b/src/V3EmitMk.cpp
@@ -65,6 +65,10 @@ public:
         of.puts("VM_TRACE = ");
         of.puts(v3Global.opt.trace() ? "1" : "0");
         of.puts("\n");
+        of.puts("# Tracing output mode in VCD format?  0/1 (from --trace)\n");
+        of.puts("VM_TRACE_VCD = ");
+        of.puts(v3Global.opt.trace() && v3Global.opt.traceFormat().vcd() ? "1" : "0");
+        of.puts("\n");
         of.puts("# Tracing output mode in FST format?  0/1 (from --trace-fst)\n");
         of.puts("VM_TRACE_FST = ");
         of.puts(v3Global.opt.trace() && v3Global.opt.traceFormat().fst() ? "1" : "0");
diff --git a/src/V3Options.h b/src/V3Options.h
index 8c185d4ea..35a71ed31 100644
--- a/src/V3Options.h
+++ b/src/V3Options.h
@@ -137,6 +137,7 @@ public:
         : m_e(static_cast<en>(_e)) {}  // Need () or GCC 4.8 false warning
     operator en() const { return m_e; }
     bool fst() const { return m_e == FST; }
+    bool vcd() const { return m_e == VCD; }
     string classBase() const {
         static const char* const names[] = {"VerilatedVcd", "VerilatedFst"};
         return names[m_e];

From ffc1c515266b2ddffd2356560a0812ade3523e06 Mon Sep 17 00:00:00 2001
From: Geza Lore <gezalore@gmail.com>
Date: Fri, 20 May 2022 16:06:38 +0100
Subject: [PATCH 19/23] Commentary

---
 Changes | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Changes b/Changes
index 7473530d0..10a8f44fe 100644
--- a/Changes
+++ b/Changes
@@ -18,6 +18,7 @@ Verilator 4.223 devel
 * Define VM_TRACE_VCD when tracing in VCD format. [Geza Lore, Shunyao CAD]
 * Fix hang with large case statement optimization (#3405). [Mike Urbach]
 * Fix 'with' operator with type casting (#3387). [xiak95]
+* Fix incorrect conditional merging (#3409). [Raynard Qiao]
 
 
 Verilator 4.222 2022-05-02

From c7610ed0448ec151b8a0ed2d299264d96715898e Mon Sep 17 00:00:00 2001
From: Geza Lore <gezalore@gmail.com>
Date: Fri, 20 May 2022 16:58:12 +0100
Subject: [PATCH 20/23] Fix FST tracing thread in CMake build

---
 Changes                   | 1 +
 src/V3EmitCMake.cpp       | 5 ++++-
 verilator-config.cmake.in | 5 +++++
 3 files changed, 10 insertions(+), 1 deletion(-)

diff --git a/Changes b/Changes
index 10a8f44fe..390606387 100644
--- a/Changes
+++ b/Changes
@@ -19,6 +19,7 @@ Verilator 4.223 devel
 * Fix hang with large case statement optimization (#3405). [Mike Urbach]
 * Fix 'with' operator with type casting (#3387). [xiak95]
 * Fix incorrect conditional merging (#3409). [Raynard Qiao]
+* Fix passing VL_TRACE_FST_WRITER_THREAD in CMake build. [Geza Lore, Shunyao CAD]
 
 
 Verilator 4.222 2022-05-02
diff --git a/src/V3EmitCMake.cpp b/src/V3EmitCMake.cpp
index 26f42e803..67e8a741c 100644
--- a/src/V3EmitCMake.cpp
+++ b/src/V3EmitCMake.cpp
@@ -114,7 +114,10 @@ class CMakeEmitter final {
         *of << "# Threaded output mode?  0/1/N threads (from --threads)\n";
         cmake_set_raw(*of, name + "_THREADS", cvtToStr(v3Global.opt.threads()));
         *of << "# Threaded tracing output mode?  0/1/N threads (from --trace-threads)\n";
-        cmake_set_raw(*of, name + "_TRACE_THREADS", cvtToStr(v3Global.opt.traceThreads()));
+        cmake_set_raw(*of, name + "_TRACE_THREADS",
+                      cvtToStr(v3Global.opt.useTraceOffloadThread()));
+        cmake_set_raw(*of, name + "_TRACE_FST_WRITER_THREAD",
+                      v3Global.opt.traceThreads() && v3Global.opt.traceFormat().fst() ? "1" : "0");
         *of << "# Struct output mode?  0/1 (from --trace-structs)\n";
         cmake_set_raw(*of, name + "_TRACE_STRUCTS", cvtToStr(v3Global.opt.traceStructs()));
         *of << "# VCD Tracing output mode?  0/1 (from --trace)\n";
diff --git a/verilator-config.cmake.in b/verilator-config.cmake.in
index 7573d29ae..7f9ece972 100644
--- a/verilator-config.cmake.in
+++ b/verilator-config.cmake.in
@@ -266,6 +266,10 @@ function(verilate TARGET)
     set_property(TARGET ${TARGET} PROPERTY VERILATOR_TRACE_THREADED ON)
   endif()
 
+  if (${VERILATE_PREFIX}_TRACE_FST_WRITER_THREAD)
+    set_property(TARGET ${TARGET} PROPERTY VERILATOR_TRACE_FST_WRITER_TRHEAD ON)
+  endif()
+
   if (${VERILATE_PREFIX}_COVERAGE)
     # If any verilate() call specifies COVERAGE, define VM_COVERAGE in the final build
     set_property(TARGET ${TARGET} PROPERTY VERILATOR_COVERAGE ON)
@@ -327,6 +331,7 @@ function(verilate TARGET)
     VM_SC=$<BOOL:$<TARGET_PROPERTY:VERILATOR_SYSTEMC>>
     $<$<BOOL:$<TARGET_PROPERTY:VERILATOR_THREADED>>:VL_THREADED>
     $<$<BOOL:$<TARGET_PROPERTY:VERILATOR_TRACE_THREADED>>:VL_TRACE_THREADED>
+    $<$<BOOL:$<TARGET_PROPERTY:VERILATOR_TRACE_FST_WRITER_TRHEAD>>:VL_TRACE_FST_WRITER_THREAD>
     VM_TRACE=$<BOOL:$<TARGET_PROPERTY:VERILATOR_TRACE>>
     VM_TRACE_VCD=$<BOOL:$<TARGET_PROPERTY:VERILATOR_TRACE_VCD>>
     VM_TRACE_FST=$<BOOL:$<TARGET_PROPERTY:VERILATOR_TRACE_FST>>

From 1282548a1c4d89f95e720892c00895010f61b1e4 Mon Sep 17 00:00:00 2001
From: Geza Lore <gezalore@gmail.com>
Date: Fri, 20 May 2022 17:55:34 +0100
Subject: [PATCH 21/23] Only consider definitions in t_flag_csplit

---
 test_regress/t/t_flag_csplit.pl | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/test_regress/t/t_flag_csplit.pl b/test_regress/t/t_flag_csplit.pl
index bef212f13..c35017122 100755
--- a/test_regress/t/t_flag_csplit.pl
+++ b/test_regress/t/t_flag_csplit.pl
@@ -87,7 +87,7 @@ sub check_cpp {
     my $fh = IO::File->new("<$filename") or error("$! $filenme");
     my @funcs;
     while (defined(my $line = $fh->getline)) {
-        if ($line =~ /^(void|IData)\s+(.*::.*)/) {
+        if ($line =~ /^(void|IData)\s+(.*::.*){/) {
             my $func = $2;
             $func =~ s/\(.*$//;
             print "\tFunc $func\n" if $Self->{verbose};

From 530817191e88adbafe5152e85621abedd136399a Mon Sep 17 00:00:00 2001
From: Wilson Snyder <wsnyder@wsnyder.org>
Date: Wed, 25 May 2022 00:50:50 -0400
Subject: [PATCH 22/23] Support non-ANSI interface port declarations (#3439).

---
 Changes                             |  1 +
 src/V3LinkDot.cpp                   |  6 ++--
 src/verilog.y                       | 44 ++++++++++++++++++++---------
 test_regress/t/t_interface_nansi.pl | 21 ++++++++++++++
 test_regress/t/t_interface_nansi.v  | 37 ++++++++++++++++++++++++
 5 files changed, 92 insertions(+), 17 deletions(-)
 create mode 100755 test_regress/t/t_interface_nansi.pl
 create mode 100644 test_regress/t/t_interface_nansi.v

diff --git a/Changes b/Changes
index 390606387..d6067565d 100644
--- a/Changes
+++ b/Changes
@@ -16,6 +16,7 @@ Verilator 4.223 devel
 * Support compile time trace signal selection with tracing_on/off (#3323). [Shunyao CAD]
 * Add assert when VerilatedContext is mis-deleted (#3121). [Rupert Swarbrick]
 * Define VM_TRACE_VCD when tracing in VCD format. [Geza Lore, Shunyao CAD]
+* Support non-ANSI interface port declarations (#3439). [Geza Lore, Shunyao CAD]
 * Fix hang with large case statement optimization (#3405). [Mike Urbach]
 * Fix 'with' operator with type casting (#3387). [xiak95]
 * Fix incorrect conditional merging (#3409). [Raynard Qiao]
diff --git a/src/V3LinkDot.cpp b/src/V3LinkDot.cpp
index 22f4d97ca..63a4eb301 100644
--- a/src/V3LinkDot.cpp
+++ b/src/V3LinkDot.cpp
@@ -1478,11 +1478,11 @@ private:
         // Need to set pin numbers after varnames are created
         // But before we do the final resolution based on names
         VSymEnt* const foundp = m_statep->getNodeSym(m_modp)->findIdFlat(nodep->name());
-        AstVar* const refp = foundp ? VN_AS(foundp->nodep(), Var) : nullptr;
-        if (!refp) {
+        AstVar* const refp = foundp ? VN_CAST(foundp->nodep(), Var) : nullptr;
+        if (!foundp) {
             nodep->v3error(
                 "Input/output/inout declaration not found for port: " << nodep->prettyNameQ());
-        } else if (!refp->isIO() && !refp->isIfaceRef()) {
+        } else if (!refp || (!refp->isIO() && !refp->isIfaceRef())) {
             nodep->v3error("Pin is not an in/out/inout/interface: " << nodep->prettyNameQ());
         } else {
             if (refp->user4()) {
diff --git a/src/verilog.y b/src/verilog.y
index a31704545..af2b427d3 100644
--- a/src/verilog.y
+++ b/src/verilog.y
@@ -104,6 +104,27 @@ public:
         string newtext = deQuote(fileline, text);
         return new AstText(fileline, newtext);
     }
+    AstNode* createCellOrIfaceRef(FileLine* fileline, const string& name, AstPin* pinlistp, AstNodeRange* rangelistp) {
+        // Must clone m_instParamp as may be comma'ed list of instances
+        VSymEnt* const foundp = SYMP->symCurrentp()->findIdFallback(name);
+        if (foundp && VN_IS(foundp->nodep(), Port)) {
+            // It's a non-ANSI interface, not a cell declaration
+            m_varAttrp = nullptr;
+            m_varDecl = VVarType::IFACEREF;
+            m_varIO = VDirection::NONE;
+            m_varLifetime = VLifetime::NONE;
+            setDType(new AstIfaceRefDType{fileline, "", GRAMMARP->m_instModule});
+            m_varDeclTyped = true;
+            AstVar* const nodep = createVariable(fileline, name, rangelistp, nullptr);
+            return nodep;
+        }
+        AstCell* const nodep = new AstCell{fileline, GRAMMARP->m_instModuleFl,
+                         name, GRAMMARP->m_instModule, pinlistp,
+                         AstPin::cloneTreeNull(GRAMMARP->m_instParamp, true),
+                                           GRAMMARP->scrubRange(rangelistp)};
+        nodep->trace(GRAMMARP->allTracingOn(fileline));
+        return nodep;
+    }
     AstDisplay* createDisplayError(FileLine* fileline) {
         AstDisplay* nodep = new AstDisplay(fileline, VDisplayType::DT_ERROR, "", nullptr, nullptr);
         nodep->addNext(new AstStop(fileline, true));
@@ -1418,8 +1439,10 @@ port_declNetE:                  // IEEE: part of port_declaration, optional net
         ;
 
 portSig<nodep>:
-                id/*port*/                              { $$ = new AstPort($<fl>1,PINNUMINC(),*$1); }
-        |       idSVKwd                                 { $$ = new AstPort($<fl>1,PINNUMINC(),*$1); }
+                id/*port*/
+                        { $$ = new AstPort{$<fl>1, PINNUMINC(), *$1}; SYMP->reinsert($$); }
+        |       idSVKwd
+                        { $$ = new AstPort{$<fl>1, PINNUMINC(), *$1}; SYMP->reinsert($$); }
         ;
 
 //**********************************************************************
@@ -2869,18 +2892,11 @@ instnameList<nodep>:
         |       instnameList ',' instnameParen          { $$ = $1->addNext($3); }
         ;
 
-instnameParen<cellp>:
-        //                      // Must clone m_instParamp as may be comma'ed list of instances
-                id instRangeListE '(' cellpinList ')'   { $$ = new AstCell($<fl>1, GRAMMARP->m_instModuleFl,
-                                                                           *$1, GRAMMARP->m_instModule, $4,
-                                                                           AstPin::cloneTreeNull(GRAMMARP->m_instParamp, true),
-                                                                           GRAMMARP->scrubRange($2));
-                                                          $$->trace(GRAMMARP->allTracingOn($<fl>1)); }
-        |       id instRangeListE                       { $$ = new AstCell($<fl>1, GRAMMARP->m_instModuleFl,
-                                                                           *$1, GRAMMARP->m_instModule, nullptr,
-                                                                           AstPin::cloneTreeNull(GRAMMARP->m_instParamp, true),
-                                                                           GRAMMARP->scrubRange($2));
-                                                          $$->trace(GRAMMARP->allTracingOn($<fl>1)); }
+instnameParen<nodep>:
+                id instRangeListE '(' cellpinList ')'
+                        { $$ = GRAMMARP->createCellOrIfaceRef($<fl>1, *$1, $4, $2); }
+        |       id instRangeListE
+                        { $$ = GRAMMARP->createCellOrIfaceRef($<fl>1, *$1, nullptr, $2); }
         //UNSUP instRangeListE '(' cellpinList ')'      { UNSUP } // UDP
         //                      // Adding above and switching to the Verilog-Perl syntax
         //                      // causes a shift conflict due to use of idClassSel inside exprScope.
diff --git a/test_regress/t/t_interface_nansi.pl b/test_regress/t/t_interface_nansi.pl
new file mode 100755
index 000000000..f60fd309f
--- /dev/null
+++ b/test_regress/t/t_interface_nansi.pl
@@ -0,0 +1,21 @@
+#!/usr/bin/env perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003-2009 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+scenarios(simulator => 1);
+
+compile(
+    );
+
+execute(
+    check_finished => 1,
+    );
+
+ok(1);
+1;
diff --git a/test_regress/t/t_interface_nansi.v b/test_regress/t/t_interface_nansi.v
new file mode 100644
index 000000000..ef9d2d418
--- /dev/null
+++ b/test_regress/t/t_interface_nansi.v
@@ -0,0 +1,37 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2022 by Geza Lore.
+// SPDX-License-Identifier: CC0-1.0
+
+interface iface(input logic clk);
+   logic [31:0] d = 0;
+   logic [31:0] q = 0;
+endinterface
+
+module mod(a);
+   iface a; // This is not a CELL, it is a port declaration
+   always @(posedge a.clk) a.q <= a.d;
+endmodule
+
+module t(clk);
+   input clk;
+
+   iface iface_inst(clk);
+   mod   mod_inst(iface_inst);
+
+   int   cyc = 0;
+
+   always @(posedge clk) begin
+      iface_inst.d <= cyc;
+      if (cyc > 1 && iface_inst.q != cyc - 2) $stop;
+   end
+
+   always @(posedge clk) begin
+      cyc <= cyc + 1;
+      if (cyc == 100) begin
+         $write("*-* All Finished *-*\n");
+         $finish;
+      end
+   end
+endmodule

From a372e010bda869f0768c2de86729ea2103001a87 Mon Sep 17 00:00:00 2001
From: github action <action@example.com>
Date: Wed, 25 May 2022 04:51:51 +0000
Subject: [PATCH 23/23] Apply 'make format'

---
 src/verilog.y | 12 ++++++++----
 1 file changed, 8 insertions(+), 4 deletions(-)

diff --git a/src/verilog.y b/src/verilog.y
index af2b427d3..ea4161500 100644
--- a/src/verilog.y
+++ b/src/verilog.y
@@ -104,7 +104,8 @@ public:
         string newtext = deQuote(fileline, text);
         return new AstText(fileline, newtext);
     }
-    AstNode* createCellOrIfaceRef(FileLine* fileline, const string& name, AstPin* pinlistp, AstNodeRange* rangelistp) {
+    AstNode* createCellOrIfaceRef(FileLine* fileline, const string& name, AstPin* pinlistp,
+                                  AstNodeRange* rangelistp) {
         // Must clone m_instParamp as may be comma'ed list of instances
         VSymEnt* const foundp = SYMP->symCurrentp()->findIdFallback(name);
         if (foundp && VN_IS(foundp->nodep(), Port)) {
@@ -118,9 +119,12 @@ public:
             AstVar* const nodep = createVariable(fileline, name, rangelistp, nullptr);
             return nodep;
         }
-        AstCell* const nodep = new AstCell{fileline, GRAMMARP->m_instModuleFl,
-                         name, GRAMMARP->m_instModule, pinlistp,
-                         AstPin::cloneTreeNull(GRAMMARP->m_instParamp, true),
+        AstCell* const nodep = new AstCell{fileline,
+                                           GRAMMARP->m_instModuleFl,
+                                           name,
+                                           GRAMMARP->m_instModule,
+                                           pinlistp,
+                                           AstPin::cloneTreeNull(GRAMMARP->m_instParamp, true),
                                            GRAMMARP->scrubRange(rangelistp)};
         nodep->trace(GRAMMARP->allTracingOn(fileline));
         return nodep;