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Fix WIDTH warning on </<= of narrower value, #2141.

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Wilson Snyder 2020-01-28 20:10:10 -05:00
parent 027cce35c0
commit d4614c290e
5 changed files with 38 additions and 3 deletions
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@ -35,6 +35,8 @@ The contributors that suggested a given feature are shown in []. Thanks!
**** Fix FST tracing of enums inside structs. [fsiegle]
**** Fix WIDTH warning on </<= of narrower value, #2141. [agrobman]
* Verilator 4.026 2020-01-11

17
src/V3Width.cpp
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@ -3517,10 +3517,23 @@ private:
int ewidth = std::max(nodep->lhsp()->widthMin(), nodep->rhsp()->widthMin());
AstNodeDType* subDTypep = nodep->findLogicDType(width, ewidth,
AstNumeric::fromBool(signedFl));
bool warnOn = true;
if (!signedFl && width == 32) {
// Waive on unsigned < or <= if RHS is narrower, since can't give wrong answer
if ((VN_IS(nodep, Lt) || VN_IS(nodep, Lte))
&& (nodep->lhsp()->width() >= nodep->rhsp()->widthMin())) {
warnOn = false;
}
// Waive on unsigned > or >= if RHS is wider, since can't give wrong answer
if ((VN_IS(nodep, Gt) || VN_IS(nodep, Gte))
&& (nodep->lhsp()->widthMin() >= nodep->rhsp()->width())) {
warnOn = false;
}
}
iterateCheck(nodep, "LHS", nodep->lhsp(), CONTEXT, FINAL, subDTypep,
signedFl ? EXTEND_LHS:EXTEND_ZERO);
(signedFl ? EXTEND_LHS : EXTEND_ZERO), warnOn);
iterateCheck(nodep, "RHS", nodep->rhsp(), CONTEXT, FINAL, subDTypep,
signedFl ? EXTEND_LHS:EXTEND_ZERO);
(signedFl ? EXTEND_LHS : EXTEND_ZERO), warnOn);
}
nodep->dtypeSetLogicBool();
}

6
test_regress/t/t_lint_width.v
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@ -12,4 +12,10 @@ module t ();
wire [4:0] sumb = 1'b1 + five;
wire [4:0] sumc = five - 1'b1;
// Relatively harmless < or <= compared with something less wide
localparam [1:0] THREE = 3;
int a;
initial for (a = 0; a < THREE; ++a) $display(a);
initial for (a = 0; a <= THREE; ++a) $display(a);
endmodule

10
test_regress/t/t_lint_width_bad.out
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@ -3,7 +3,7 @@
localparam [3:0] XS = 'hx;
^~
... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.
%Warning-WIDTH: t/t_lint_width_bad.v:38: Operator ASSIGNW expects 5 bits on the Assign RHS, but Assign RHS's VARREF 'in' generates 4 bits.
%Warning-WIDTH: t/t_lint_width_bad.v:44: Operator ASSIGNW expects 5 bits on the Assign RHS, but Assign RHS's VARREF 'in' generates 4 bits.
: ... In instance t.p4
wire [4:0] out = in;
^
@ -31,4 +31,12 @@
: ... In instance t
wire [2:0] cnt = (one + one + one + one);
^
%Warning-WIDTH: t/t_lint_width_bad.v:36: Operator GT expects 41 bits on the LHS, but LHS's VARREF 'a' generates 32 bits.
: ... In instance t
initial for (a = 0; a > THREE; ++a) $display(a);
^
%Warning-WIDTH: t/t_lint_width_bad.v:37: Operator GTE expects 41 bits on the LHS, but LHS's VARREF 'a' generates 32 bits.
: ... In instance t
initial for (a = 0; a >= THREE; ++a) $display(a);
^~
%Error: Exiting due to

6
test_regress/t/t_lint_width_bad.v
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@ -30,6 +30,12 @@ module t ();
wire one = 1;
wire [2:0] cnt = (one + one + one + one);
// Not harmless > or >= compared with something wider (as different results if "a" wider)
localparam [40:0] THREE = 3;
int a;
initial for (a = 0; a > THREE; ++a) $display(a);
initial for (a = 0; a >= THREE; ++a) $display(a);
endmodule
module p