Fix internal error on unconnected inouts, bug1187.

Changes

@@ -14,6 +14,8 @@ The contributors that suggested a given feature are shown in []. Thanks!
 
 ****  Fix undefined VL_POW_WWI. [Clifford Wolf]
 
+****  Fix internal error on unconnected inouts, bug1187. [Rob Stoddard]
+
 
 * Verilator 3.906 2017-06-22
 

src/V3Tristate.cpp

@@ -1074,7 +1074,8 @@ class TristateVisitor : public TristateBaseVisitor {
 		UINFO(5,"Unconnected pin terminate "<<nodep<<endl);
 		AstVar* ucVarp = getCreateUnconnVarp(nodep, nodep->modVarp()->dtypep());
 		nodep->exprp(new AstVarRef(nodep->fileline(), ucVarp,
-					   nodep->modVarp()->isOutput()));
+					   // We converted, so use declaration output state
+					   nodep->modVarp()->isDeclOutput()));
 		m_tgraph.setTristate(ucVarp);
 		// We don't need a driver on the wire; the lack of one will default to tristate
 	    } else if (inDeclProcessing) {   // Not an input that was a converted tristate

test_regress/t/t_tri_public.pl

@@ -0,0 +1,15 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+
+# Compile only test
+compile (
+    );
+
+ok(1);
+1;

test_regress/t/t_tri_public.v

@@ -0,0 +1,78 @@
+// DESCRIPTION: Verilator: Unsupported tristate constructur error
+//
+// This is a compile only regression test of tristate handling for bug514
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2017 by Rob Stoddard.
+
+module t (/*AUTOARG*/
+   // Outputs
+   out,
+   // Inputs
+   data, up_down, clk, reset
+   );
+
+   //----------Output Ports--------------
+   output [7:0] out;
+   //------------Input Ports--------------
+   //input [7:0] data ;
+   input [7:0] 	data;
+   input 	up_down, clk, reset;
+   //------------Internal Variables--------
+   reg [7:0] 	out;
+   logic [7:0] 	q_out;
+
+   //-------------Code Starts Here-------
+   always @(posedge clk)
+     if (reset) begin // active high reset
+        out <= 8'b0 ;
+     end else if (up_down) begin
+        out <= out + 1;
+     end else begin
+        out <= q_out;
+     end
+
+   // verilator lint_off PINMISSING
+   sub_mod sub_mod
+     (
+      .clk(clk),
+      .data(data),
+      .reset(reset),
+      .q(q_out)
+      );
+   // verilator lint_on PINMISSING
+
+endmodule
+
+module sub_mod (/*AUTOARG*/
+   // Outputs
+   q, test_out,
+   // Inouts
+   test_inout,
+   // Inputs
+   data, clk, reset
+   );
+
+   //-----------Input Ports---------------
+
+   input [7:0] data /*verilator public*/;
+   input       clk, reset;
+   inout       test_inout;  // Get rid of this, the problem goes away.
+
+   //-----------Output Ports---------------
+   output [7:0] q;
+   output 	test_out;  // Not assigned,  no problem.
+
+   logic [7:0] 	que;
+
+   // Uncomment this line, the error goes away.
+   //assign test_inout = que;
+
+   assign q = que;
+   always @ ( posedge clk)
+     if (~reset) begin
+        que <= 8'b0;
+     end else begin
+        que <= data;
+     end
+endmodule