From d43e9aa2c5d7c56c8af2b75e85edf06902661407 Mon Sep 17 00:00:00 2001
From: Wilson Snyder <wsnyder@wsnyder.org>
Date: Sat, 29 Jun 2019 11:28:22 -0400
Subject: [PATCH] Fix not in array context on non-power-of-two slices, msg2946.

---
 Changes                      |  2 ++
 src/V3Unknown.cpp            |  3 ++-
 test_regress/t/t_array_mda.v | 12 ++----------
 3 files changed, 6 insertions(+), 11 deletions(-)

diff --git a/Changes b/Changes
index 3a72014e3..943cbebcf 100644
--- a/Changes
+++ b/Changes
@@ -8,6 +8,8 @@ The contributors that suggested a given feature are shown in []. Thanks!
 
 ****  Fix not reporting some duplicate signals/ports, bug1462. [Peter Gerst]
 
+****  Fix not in array context on non-power-of-two slices, msg2946. [Yu Sheng Lin]
+
 
 * Verilator 4.016 2016-06-16
 
diff --git a/src/V3Unknown.cpp b/src/V3Unknown.cpp
index f261cb7b2..70a0cb7fa 100644
--- a/src/V3Unknown.cpp
+++ b/src/V3Unknown.cpp
@@ -411,7 +411,8 @@ private:
                 condp->deleteTree();
             }
             else if (!lvalue
-                     && !VN_IS(nodep->backp(), ArraySel)) {  // Too complicated and slow if mid-multidimension
+                     // Making a scalar would break if we're making an array
+                     && !VN_IS(nodep->dtypep()->skipRefp(), NodeArrayDType)) {
                 // ARRAYSEL(...) -> COND(LT(bit<maxbit), ARRAYSEL(...), {width{1'bx}})
                 AstNRelinker replaceHandle;
                 nodep->unlinkFrBack(&replaceHandle);
diff --git a/test_regress/t/t_array_mda.v b/test_regress/t/t_array_mda.v
index 899714d5d..648c9b3c6 100644
--- a/test_regress/t/t_array_mda.v
+++ b/test_regress/t/t_array_mda.v
@@ -17,16 +17,8 @@ module t (/*AUTOARG*/
    int A [7][1], B [8][1];
    int a    [1], b    [1];
    always_ff @(posedge clk) begin
-`ifdef verilator  // msg2946
- `define WORK_AROUND
-`endif
-`ifdef WORK_AROUND
-      a <= A[0];
-      b <= B[crc[2:0]];
-`else
       a <= A[crc[2:0]];
-      b <= B[0];
-`endif
+      b <= B[crc[2:0]];
    end
    wire [63:0] result = {a[0], b[0]};
 
@@ -67,7 +59,7 @@ module t (/*AUTOARG*/
          $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
          if (crc !== 64'hc77bb9b3784ea091) $stop;
          // What checksum will we end up with (above print should match)
-`define EXPECTED_SUM 64'had01cfb7e84da129
+`define EXPECTED_SUM 64'h619f75c3a6d948bd
          if (sum !== `EXPECTED_SUM) $stop;
          $write("*-* All Finished *-*\n");
          $finish;