From d3a787698b6c9910697f9d195de9289d4c9db16d Mon Sep 17 00:00:00 2001
From: Todd Strader <todd.strader@gmail.com>
Date: Fri, 20 Mar 2020 08:41:58 -0400
Subject: [PATCH] Working on flattening types

---
 src/V3AstNodes.h | 33 +++++++++++++++++++++++++++++++++
 src/V3Width.cpp  | 13 +++++++++++++
 src/verilog.y    |  4 ++--
 3 files changed, 48 insertions(+), 2 deletions(-)

diff --git a/src/V3AstNodes.h b/src/V3AstNodes.h
index c060added..dc111622c 100644
--- a/src/V3AstNodes.h
+++ b/src/V3AstNodes.h
@@ -5281,6 +5281,23 @@ public:
     virtual bool sizeMattersLhs() const { return false; }
     virtual bool sizeMattersRhs() const { return false; }
 };
+class AstEqT : public AstNodeBiCom {
+public:
+    AstEqT(FileLine* fl, AstNode* lhsp, AstNode* rhsp)
+        : ASTGEN_SUPER(fl, lhsp, rhsp) { dtypeSetLogicBool(); }
+    ASTNODE_NODE_FUNCS(EqT)
+    virtual AstNode* cloneType(AstNode* lhsp, AstNode* rhsp) { return new AstEqT(this->fileline(), lhsp, rhsp); }
+    virtual void numberOperate(V3Number& out, const V3Number& lhs, const V3Number& rhs) { out.opEq(lhs, rhs); }
+    virtual string emitVerilog() { return "%k(%l %f== %r)"; }
+    // TOOD -- if we can't even emit C, should this be a child of AstNodeMath?
+    virtual string emitC() { return ""; }
+    virtual string emitSimpleOperator() { return "=="; }
+    virtual bool cleanOut() const { return false; }
+    virtual bool cleanLhs() const { return false; }
+    virtual bool cleanRhs() const { return false; }
+    virtual bool sizeMattersLhs() const { return false; }
+    virtual bool sizeMattersRhs() const { return false; }
+};
 class AstEqD : public AstNodeBiCom {
 public:
     AstEqD(FileLine* fl, AstNode* lhsp, AstNode* rhsp)
@@ -5333,6 +5350,22 @@ public:
     virtual bool sizeMattersLhs() const { return false; }
     virtual bool sizeMattersRhs() const { return false; }
 };
+class AstNeqT : public AstNodeBiCom {
+public:
+    AstNeqT(FileLine* fl, AstNode* lhsp, AstNode* rhsp)
+        : ASTGEN_SUPER(fl, lhsp, rhsp) { dtypeSetLogicBool(); }
+    ASTNODE_NODE_FUNCS(NeqT)
+    virtual AstNode* cloneType(AstNode* lhsp, AstNode* rhsp) { return new AstNeqT(this->fileline(), lhsp, rhsp); }
+    virtual void numberOperate(V3Number& out, const V3Number& lhs, const V3Number& rhs) { out.opNeq(lhs, rhs); }
+    virtual string emitVerilog() { return "%k(%l %f!= %r)"; }
+    virtual string emitC() { return ""; }
+    virtual string emitSimpleOperator() { return "!="; }
+    virtual bool cleanOut() const { return false; }
+    virtual bool cleanLhs() const { return false; }
+    virtual bool cleanRhs() const { return false; }
+    virtual bool sizeMattersLhs() const { return false; }
+    virtual bool sizeMattersRhs() const { return false; }
+};
 class AstNeqD : public AstNodeBiCom {
 public:
     AstNeqD(FileLine* fl, AstNode* lhsp, AstNode* rhsp)
diff --git a/src/V3Width.cpp b/src/V3Width.cpp
index 485dbd7e0..545ddfaf8 100644
--- a/src/V3Width.cpp
+++ b/src/V3Width.cpp
@@ -254,6 +254,9 @@ private:
     // ...    These comparisons don't allow reals
     virtual void visit(AstEqWild* nodep) VL_OVERRIDE {      visit_cmp_eq_gt(nodep, false); }
     virtual void visit(AstNeqWild* nodep) VL_OVERRIDE {     visit_cmp_eq_gt(nodep, false); }
+    // ...    Type compares
+    virtual void visit(AstEqT* nodep) VL_OVERRIDE {         visit_cmp_eq_type(nodep); }
+    virtual void visit(AstNeqT* nodep) VL_OVERRIDE {        visit_cmp_eq_type(nodep); }
     // ...    Real compares
     virtual void visit(AstEqD* nodep) VL_OVERRIDE {         visit_cmp_real(nodep); }
     virtual void visit(AstNeqD* nodep) VL_OVERRIDE {        visit_cmp_real(nodep); }
@@ -3571,6 +3574,16 @@ private:
         }
     }
 
+    void visit_cmp_eq_type(AstNodeBiop* nodep) {
+        if (m_vup->prelim()) {
+            userIterateAndNext(nodep->lhsp(), WidthVP(CONTEXT, PRELIM).p());
+            userIterateAndNext(nodep->rhsp(), WidthVP(CONTEXT, PRELIM).p());
+            // TODO -- remove
+            UINFO(1,"Type comparision LHS : "<<nodep->lhsp()<<endl);
+            UINFO(1,"Type comparision RHS : "<<nodep->rhsp()<<endl);
+        }
+    }
+
     void visit_cmp_eq_gt(AstNodeBiop* nodep, bool realok) {
         // CALLER: AstEq, AstGt, ..., AstLtS
         // Real allowed if and only if real_lhs set
diff --git a/src/verilog.y b/src/verilog.y
index 878f0c9b6..c9a1c236c 100644
--- a/src/verilog.y
+++ b/src/verilog.y
@@ -3695,9 +3695,9 @@ expr<nodep>:			// IEEE: part of expression/constant_expression/primary
 	|	~l~expr '*' ~r~expr			{ $$ = new AstMul	($2,$1,$3); }
 	|	~l~expr '/' ~r~expr			{ $$ = new AstDiv	($2,$1,$3); }
 	|	~l~expr '%' ~r~expr			{ $$ = new AstModDiv	($2,$1,$3); }
-	|	type_reference yP_EQUAL type_reference	{ $$ = new AstEq	($2,$1,$3); }
+	|	type_reference yP_EQUAL type_reference	{ $$ = new AstEqT	($2,$1,$3); }
 	|	~l~expr yP_EQUAL ~r~expr		{ $$ = new AstEq	($2,$1,$3); }
-	|	type_reference yP_NOTEQUAL type_reference { $$ = new AstNeq	($2,$1,$3); }
+	|	type_reference yP_NOTEQUAL type_reference { $$ = new AstNeqT	($2,$1,$3); }
 	|	~l~expr yP_NOTEQUAL ~r~expr		{ $$ = new AstNeq	($2,$1,$3); }
 	|	~l~expr yP_CASEEQUAL ~r~expr		{ $$ = new AstEqCase	($2,$1,$3); }
 	|	~l~expr yP_CASENOTEQUAL ~r~expr		{ $$ = new AstNeqCase	($2,$1,$3); }