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Fix display has no time units on class function (#3116).

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This commit is contained in:
Wilson Snyder 2021-09-08 19:31:26 -04:00
parent a8b480559d
commit d384a69877
6 changed files with 16 additions and 4 deletions
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1
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@ -13,6 +13,7 @@ Verilator 4.213 devel
* Include processor information in verilator_gantt data file. * Include processor information in verilator_gantt data file.
* Fix verilator_profcfunc profile accounting (#3115). * Fix verilator_profcfunc profile accounting (#3115).
* Fix display has no time units on class function (#3116). [Damien Pretet]
Verilator 4.212 2021-09-01 Verilator 4.212 2021-09-01

2
src/V3AstNodes.cpp
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@ -1338,7 +1338,7 @@ void AstNodeCoverOrAssert::dump(std::ostream& str) const {
} }
void AstDisplay::dump(std::ostream& str) const { void AstDisplay::dump(std::ostream& str) const {
this->AstNodeStmt::dump(str); this->AstNodeStmt::dump(str);
// str<<" "<<displayType().ascii(); // str << " " << displayType().ascii();
} }
void AstEnumItemRef::dump(std::ostream& str) const { void AstEnumItemRef::dump(std::ostream& str) const {
this->AstNodeMath::dump(str); this->AstNodeMath::dump(str);

2
src/V3LinkLevel.cpp
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@ -132,6 +132,8 @@ void V3LinkLevel::timescaling(const ModVec& mods) {
v3Global.rootp()->timeprecisionMerge(v3Global.rootp()->fileline(), v3Global.rootp()->timeprecisionMerge(v3Global.rootp()->fileline(),
VTimescale(VTimescale::TS_DEFAULT)); VTimescale(VTimescale::TS_DEFAULT));
} }
// Classes under package have timescale propaged in V3LinkParse
} }
//###################################################################### //######################################################################

3
src/V3LinkParse.cpp
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@ -504,7 +504,8 @@ private:
{ {
// Module: Create sim table for entire module and iterate // Module: Create sim table for entire module and iterate
cleanFileline(nodep); cleanFileline(nodep);
// // Classes inherit from upper package
if (m_modp && nodep->timeunit().isNone()) nodep->timeunit(m_modp->timeunit());
m_modp = nodep; m_modp = nodep;
m_genblkAbove = 0; m_genblkAbove = 0;
m_genblkNum = 0; m_genblkNum = 0;

5
test_regress/t/t_class_format.out
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@ -1,3 +1,4 @@
''{b:'h1, i:'h2a, carray4:'{'h11, 'h22, 'h33, 'h44} }' ''{b:'h1, i:'h2a, carray4:'{'h11, 'h22, 'h33, 'h44} , name:"object_name"}'
''{b:'h1, i:'h2a, carray4:'{'h911, 'h922, 'h933, 'h944} }' ''{b:'h1, i:'h2a, carray4:'{'h911, 'h922, 'h933, 'h944} , name:"object_name"}'
DEBUG: object_name (@0) message
*-* All Finished *-* *-* All Finished *-*

7
test_regress/t/t_class_format.v
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@ -15,6 +15,10 @@ class Cls;
bit b; bit b;
int i; int i;
bit [15:0] carray4 [4]; bit [15:0] carray4 [4];
string name;
task debug();
$display("DEBUG: %s (@%0t) %s", this.name, $realtime, "message");
endtask
endclass endclass
module t (/*AUTOARG*/); module t (/*AUTOARG*/);
@ -23,6 +27,7 @@ module t (/*AUTOARG*/);
c = new; c = new;
c.b = '1; c.b = '1;
c.i = 42; c.i = 42;
c.name = "object_name";
c.carray4[0] = 16'h11; c.carray4[0] = 16'h11;
c.carray4[1] = 16'h22; c.carray4[1] = 16'h22;
@ -33,6 +38,8 @@ module t (/*AUTOARG*/);
c.carray4 = '{16'h911, 16'h922, 16'h933, 16'h944}; c.carray4 = '{16'h911, 16'h922, 16'h933, 16'h944};
$display("'%p'", c); $display("'%p'", c);
c.debug();
$write("*-* All Finished *-*\n"); $write("*-* All Finished *-*\n");
$finish; $finish;
end end