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Fix define argument stringification, broke since 3.914.

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Wilson Snyder 2018-06-21 08:19:59 -04:00
parent 43d07235c9
commit d225e46e4a
5 changed files with 60 additions and 2 deletions
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@ -6,6 +6,8 @@ The contributors that suggested a given feature are shown in []. Thanks!
**** Add OBJCACHE envvar support to examples and generated Makefiles.
**** Fix define argument stringification (`"), broke since 3.914. [Joe DErrico]
* Verilator 3.924 2018-06-12

2
src/V3PreLex.l
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@ -208,7 +208,7 @@ drop [\032]
<ARGMODE>{crnl} { linenoInc(); yytext=(char*)"\n"; yyleng=1; return(VP_WHITE); }
<ARGMODE>{quote} { yy_push_state(STRMODE); yymore(); }
<ARGMODE>"`\\`\"" { appendDefValue(yytext,yyleng); } /* Literal text */
<ARGMODE>{tickquote} { return(VP_STRIFY); }
<ARGMODE>{tickquote} { yy_push_state(STRIFY); return(VP_STRIFY); }
<ARGMODE>[{\[] { LEXP->m_parenLevel++; appendDefValue(yytext,yyleng); }
<ARGMODE>[}\]] { LEXP->m_parenLevel--; appendDefValue(yytext,yyleng); }
<ARGMODE>[(] { LEXP->m_parenLevel++;

4
src/V3PreProc.cpp
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@ -1127,6 +1127,10 @@ int V3PreProcImp::getStateToken() {
string rtn; rtn.assign(yyourtext(),yyourleng());
refp->nextarg(refp->nextarg()+rtn);
goto next_tok;
} else if (tok==VP_STRIFY) {
// We must expand stringinfication, when done will return to this state
statePush(ps_STRIFY);
goto next_tok;
} else {
error((string)"Expecting ) or , to end argument list for define reference. Found: "+tokenName(tok));
statePop();

34
test_regress/t/t_preproc.out
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@ -899,6 +899,38 @@ XYS_FAMILY = XYS_foo
`line 614 "t/t_preproc.v" 0
`line 617 "t/t_preproc.v" 0
`dbg_hdl(UVM_LOW, ("Functional coverage enabled: paramgrp"));
`line 620 "t/t_preproc.v" 0
`line 628 "t/t_preproc.v" 0
module pcc2_cfg;
generate
`line 630 "t/t_preproc.v" 0
covergroup a @(posedge b);
`line 630 "t/t_preproc.v" 0
c: coverpoint d iff ((c) === 1'b1); endgroup
`line 630 "t/t_preproc.v" 0
a u_a;
`line 630 "t/t_preproc.v" 0
initial do begin $display ("DEBUG : %s [%m]", $sformatf ("Functional coverage enabled: u_a")); end while(0);
endgenerate
endmodule
`line 634 "t/t_preproc.v" 0
predef 0 0
predef 1 1
@ -917,4 +949,4 @@ predef 1 1
predef 2 2
`line 634 "t/t_preproc.v" 2
`line 654 "t/t_preproc.v" 2

20
test_regress/t/t_preproc.v
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@ -611,6 +611,26 @@ NYS_FAMILY = `NYS_FAMILY
`define INSTANCE(NAME) (.mySig (myInterface.``NAME),
`INSTANCE(pa5)
//======================================================================
// Stringify bug
`define hack(GRP) `dbg_hdl(UVM_LOW, (`"Functional coverage enabled: GRP`"));
`hack(paramgrp)
`define dbg_hdl(LVL, MSG) $display ("DEBUG : %s [%m]", $sformatf MSG)
`define svfcov_new(GRP) \
initial do begin `dbg_hdl(UVM_LOW, (`"Functional coverage enabled: GRP`")); end while(0)
`define simple_svfcov_clk(LBL, CLK, RST, ARG) \
covergroup LBL @(posedge CLK); \
c: coverpoint ARG iff ((RST) === 1'b1); endgroup \
LBL u_``LBL; `svfcov_new(u_``LBL)
module pcc2_cfg;
generate
`simple_svfcov_clk(a, b, c, d);
endgenerate
endmodule
//======================================================================
// IEEE mandated predefines
`undefineall // undefineall should have no effect on these