forked from github/verilator
Fix regression due to early constant folding in +: and -: (#2338)
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@ -458,6 +458,7 @@ private:
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UINFO(6, "SELPLUS/MINUS " << nodep << endl);
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// Below 2 lines may change nodep->widthp()
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if (debug() >= 9) nodep->dumpTree(cout, "--SELPM0: ");
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V3Width::widthParamsEdit(nodep->rhsp()); // constifyEdit doesn't ensure widths finished
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V3Const::constifyEdit(nodep->rhsp()); // May relink pointed to node, ok if not const
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V3Const::constifyParamsEdit(nodep->thsp()); // May relink pointed to node
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checkConstantOrReplace(nodep->thsp(), "Width of :+ or :- bit extract isn't a constant");
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@ -74,4 +74,19 @@ module t (/*AUTOARG*/
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endcase
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end
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// Additional constant folding check - this used to trigger a bug
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reg [23:0] a;
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reg [3:0] b;
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initial begin
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a = 24'd0;
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b = 4'b0111;
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a[3*(b[2:0]+0)+:3] = 3'd7; // Check LSB expression goes to 32-bits
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if (a != 24'b11100000_00000000_00000000) $stop;
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a = 24'd0;
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b = 4'b0110;
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a[3*(b[2:0]+0)-:3] = 3'd7; // Check MSB expression goes to 32-bits
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if (a != 24'b00000111_00000000_00000000) $stop;
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end
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endmodule
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