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Parse intersect/throughout/within, still unsupported.

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This commit is contained in:
Wilson Snyder 2023-03-05 19:57:09 -05:00
parent cb89ef9885
commit d0f5ce0cc4
7 changed files with 136 additions and 19 deletions
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6
src/verilog.l
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@ -539,7 +539,7 @@ vnum {vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5}
"inside" { FL; return yINSIDE; }
"int" { FL; return yINT; }
"interface" { FL; return yINTERFACE; }
"intersect" { ERROR_RSVD_WORD("SystemVerilog 2005"); }
"intersect" { FL; return yINTERSECT; }
"join_any" { FL; return yJOIN_ANY; }
"join_none" { FL; return yJOIN_NONE; }
"local" { FL; return yLOCAL__LEX; }
@ -574,7 +574,7 @@ vnum {vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5}
"super" { FL; return ySUPER; }
"tagged" { ERROR_RSVD_WORD("SystemVerilog 2005"); }
"this" { FL; return yTHIS; }
"throughout" { ERROR_RSVD_WORD("SystemVerilog 2005"); }
"throughout" { FL; return yTHROUGHOUT; }
"timeprecision" { FL; return yTIMEPRECISION; }
"timeunit" { FL; return yTIMEUNIT; }
"type" { FL; return yTYPE__LEX; }
@ -587,7 +587,7 @@ vnum {vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5}
"wait_order" { ERROR_RSVD_WORD("SystemVerilog 2005"); }
"wildcard" { ERROR_RSVD_WORD("SystemVerilog 2005"); }
"with" { FL; return yWITH__LEX; }
"within" { ERROR_RSVD_WORD("SystemVerilog 2005"); }
"within" { FL; return yWITHIN; }
}
/* SystemVerilog 2009 */

40
src/verilog.y
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@ -645,7 +645,7 @@ BISONPRE_VERSION(3.7,%define api.header.include {"V3ParseBison.h"})
%token<fl> yINTEGER "integer"
%token<fl> yINTERCONNECT "interconnect"
%token<fl> yINTERFACE "interface"
//UNSUP %token<fl> yINTERSECT "intersect"
%token<fl> yINTERSECT "intersect"
%token<fl> yJOIN "join"
%token<fl> yJOIN_ANY "join_any"
%token<fl> yJOIN_NONE "join_none"
@ -743,7 +743,7 @@ BISONPRE_VERSION(3.7,%define api.header.include {"V3ParseBison.h"})
//UNSUP %token<fl> yTASK__LEX "task-in-lex"
//UNSUP %token<fl> yTASK__aPUREV "task-is-pure-virtual"
%token<fl> yTHIS "this"
//UNSUP %token<fl> yTHROUGHOUT "throughout"
%token<fl> yTHROUGHOUT "throughout"
%token<fl> yTIME "time"
%token<fl> yTIMEPRECISION "timeprecision"
%token<fl> yTIMEUNIT "timeunit"
@ -785,7 +785,7 @@ BISONPRE_VERSION(3.7,%define api.header.include {"V3ParseBison.h"})
%token<fl> yWHILE "while"
//UNSUP %token<fl> yWILDCARD "wildcard"
%token<fl> yWIRE "wire"
//UNSUP %token<fl> yWITHIN "within"
%token<fl> yWITHIN "within"
%token<fl> yWITH__BRA "with-then-["
%token<fl> yWITH__CUR "with-then-{"
%token<fl> yWITH__ETC "with"
@ -1072,13 +1072,13 @@ BISONPRE_VERSION(3.7,%define api.header.include {"V3ParseBison.h"})
%right yP_ORMINUSGT yP_OREQGT yP_POUNDMINUSPD yP_POUNDEQPD
%right yUNTIL yS_UNTIL yUNTIL_WITH yS_UNTIL_WITH yIMPLIES
//UNSUP %right yIFF
//UNSUP %left yOR
//UNSUP %left yAND
%right yIFF
%left yOR
%left yAND
%nonassoc yNOT yNEXTTIME yS_NEXTTIME
//UNSUP %left yINTERSECT
//UNSUP %left yWITHIN
//UNSUP %right yTHROUGHOUT
%left yINTERSECT
%left yWITHIN
%right yTHROUGHOUT
//UNSUP %left prPOUNDPOUND_MULTI
//UNSUP %left yP_POUNDPOUND
//UNSUP %left yP_BRASTAR yP_BRAEQ yP_BRAMINUSGT yP_BRAPLUSKET
@ -6053,7 +6053,8 @@ pexpr<nodeExprp>: // IEEE: property_expr (The name pexpr is important as regex
| ~o~pexpr yIMPLIES pexpr
{ $$ = $1; BBUNSUP($2, "Unsupported: implies (in property expression)"); }
// // yIFF also used by event_expression
//UNSUP ~o~pexpr yIFF ~o~pexpr { }
| ~o~pexpr yIFF pexpr
{ $$ = $1; BBUNSUP($2, "Unsupported: iff (in property expression)"); }
| yACCEPT_ON '(' expr/*expression_or_dist*/ ')' pexpr %prec yACCEPT_ON
{ $$ = $5; BBUNSUP($2, "Unsupported: accept_on (in property expression)"); }
| yREJECT_ON '(' expr/*expression_or_dist*/ ')' pexpr %prec yREJECT_ON
@ -6108,17 +6109,24 @@ sexpr<nodeExprp>: // ==IEEE: sequence_expr (The name sexpr is important as reg
//UNSUP '(' ~p~sexpr ',' sequence_match_itemList ')' { }
//
// // AND/OR are between pexprs OR sexprs
//UNSUP ~p~sexpr yAND ~p~sexpr { $$ = new AstLogAnd{$2, $1, $3}; }
//UNSUP ~p~sexpr yOR ~p~sexpr { $$ = new AstLogOr{$2, $1, $3}; }
| ~p~sexpr yAND ~p~sexpr
{ $$ = new AstLogAnd{$2, $1, $3};
BBUNSUP($2, "Unsupported: and (in sequence expression)"); }
| ~p~sexpr yOR ~p~sexpr
{ $$ = new AstLogOr{$2, $1, $3};
BBUNSUP($2, "Unsupported: or (in sequence expression)"); }
// // Intersect always has an sexpr rhs
//UNSUP ~p~sexpr yINTERSECT sexpr { $<fl>$ = $<fl>1; $$ = ...; }
| ~p~sexpr yINTERSECT sexpr
{ $$ = $1; BBUNSUP($2, "Unsupported: intersect (in sequence expression)"); }
//
//UNSUP yFIRST_MATCH '(' sexpr ')' { }
//UNSUP yFIRST_MATCH '(' sexpr ',' sequence_match_itemList ')' { }
//UNSUP ~p~sexpr/*sexpression_or_dist*/ yTHROUGHOUT sexpr { }
| ~p~sexpr/*sexpression_or_dist*/ yTHROUGHOUT sexpr
{ $$ = $1; BBUNSUP($2, "Unsupported: throughout (in sequence expression)"); }
// // Below pexpr's are really sequence_expr, but avoid conflict
// // IEEE: sexpr yWITHIN sexpr
//UNSUP ~p~sexpr yWITHIN sexpr { $<fl>$ = $<fl>1; $$ = ...; }
| ~p~sexpr yWITHIN sexpr
{ $$ = $1; BBUNSUP($2, "Unsupported: within (in sequence expression)"); }
// // Note concurrent_assertion had duplicate rule for below
//UNSUP clocking_event ~p~sexpr %prec prSEQ_CLOCKING { }
//
@ -6143,7 +6151,7 @@ sexpr<nodeExprp>: // ==IEEE: sequence_expr (The name sexpr is important as reg
//UNSUPsequence_match_itemList<nodep>: // IEEE: [sequence_match_item] part of sequence_expr
//UNSUP sequence_match_item { $$ = $1; }
//UNSUP | sequence_match_itemList ',' sequence_match_item { }
//UNSUP | sequence_match_itemList ',' sequence_match_item { $$ = addNextNull($1, $3); }
//UNSUP ;
//UNSUPsequence_match_item<nodep>: // ==IEEE: sequence_match_item

3
test_regress/t/t_assert_property_pexpr_unsup.out
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@ -89,4 +89,7 @@
%Error-UNSUPPORTED: t/t_assert_property_pexpr_unsup.v:112:22: Unsupported: sync_reject_on (in property expression)
112 | sync_reject_on (a) b;
| ^
%Error-UNSUPPORTED: t/t_assert_property_pexpr_unsup.v:116:9: Unsupported: iff (in property expression)
116 | a iff b;
| ^~~
%Error: Exiting due to

4
test_regress/t/t_assert_property_pexpr_unsup.v
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@ -112,6 +112,10 @@ module t (/*AUTOARG*/
sync_reject_on (a) b;
endproperty
property p_iff;
a iff b;
endproperty
always @(posedge clk) begin
if (cyc == 10) begin
$write("*-* All Finished *-*\n");

32
test_regress/t/t_sequence_sexpr_unsup.out Normal file
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@ -0,0 +1,32 @@
%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:25:14: Unsupported: within (in sequence expression)
25 | weak(a within(b));
| ^~~~~~
... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest
%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:25:11: Unsupported: weak (in property expression)
25 | weak(a within(b));
| ^
%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:29:14: Unsupported: and (in sequence expression)
29 | weak(a and b);
| ^~~
%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:29:11: Unsupported: weak (in property expression)
29 | weak(a and b);
| ^
%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:33:14: Unsupported: or (in sequence expression)
33 | weak(a or b);
| ^~
%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:33:11: Unsupported: weak (in property expression)
33 | weak(a or b);
| ^
%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:37:14: Unsupported: throughout (in sequence expression)
37 | weak(a throughout b);
| ^~~~~~~~~~
%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:37:11: Unsupported: weak (in property expression)
37 | weak(a throughout b);
| ^
%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:41:14: Unsupported: intersect (in sequence expression)
41 | weak(a intersect b);
| ^~~~~~~~~
%Error-UNSUPPORTED: t/t_sequence_sexpr_unsup.v:41:11: Unsupported: weak (in property expression)
41 | weak(a intersect b);
| ^
%Error: Exiting due to

20
test_regress/t/t_sequence_sexpr_unsup.pl Executable file
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@ -0,0 +1,20 @@
#!/usr/bin/env perl
if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2022 by Wilson Snyder. This program is free software; you
# can redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
scenarios(vlt => 1);
compile(
expect_filename => $Self->{golden_filename},
verilator_flags2 => ['--assert'],
fails => 1,
);
ok(1);
1;

50
test_regress/t/t_sequence_sexpr_unsup.v Normal file
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@ -0,0 +1,50 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2023 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/
// Inputs
clk, a, b
);
input clk;
int a;
int b;
int cyc = 0;
always @(posedge clk) begin
cyc <= cyc + 1;
end
// NOTE this grammar hasn't been checked with other simulators,
// is here just to avoid uncovered code lines in the grammar.
// NOTE using 'property weak' here as sequence/endsequence not supported
property s_within;
weak(a within(b));
endproperty
property s_and;
weak(a and b);
endproperty
property s_or;
weak(a or b);
endproperty
property s_throughout;
weak(a throughout b);
endproperty
property s_intersect;
weak(a intersect b);
endproperty
always @(posedge clk) begin
if (cyc == 10) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule