forked from github/verilator
Docs: Fix cross-references
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README.rst
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README.rst
@ -23,15 +23,15 @@ Welcome to Verilator
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* Compiles into multithreaded C++, or SystemC
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* Creates XML to front-end your own tools
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- |Logo|
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* - |verilator multithreaded performance bg min|
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* - |verilator multithreaded performance|
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- **Fast**
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* Outperforms many commercial simulators
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* Single- and multi-threaded output models
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* - **Widely Used**
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* Wide industry and academic deployment
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* Out-of-the-box support from Arm, and RISC-V vendor IP
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- |verilator usage 400x200 min|
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* - |verilator community 400x125 min|
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- |verilator usage|
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* - |verilator community|
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- **Community Driven & Openly Licensed**
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* Guided by the `CHIPS Alliance`_ and `Linux Foundation`_
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* Open, and free as in both speech and beer
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@ -40,7 +40,7 @@ Welcome to Verilator
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* Commercial support contracts
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* Design support contracts
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* Enhancement contracts
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- |verilator support 400x125 min|
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- |verilator support|
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What Verilator Does
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@ -85,15 +85,6 @@ Modelsim, Cadence Incisive/NC-Verilog, Synopsys VCS, VTOC, and Pragmatic
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CVer/CVC). But, Verilator is open-sourced, so you can spend on computes
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rather than licenses. Thus Verilator gives you the best cycles/dollar.
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For more information on how Verilator stacks up to some of the other
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closed-sourced and open-sourced Verilog simulators, see the `Verilog
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Simulator Benchmarks
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<https://www.veripool.org/verilog_sim_benchmarks.html>`_. (If you
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benchmark Verilator, please see the notes in the `Verilator manual (PDF)
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<https://verilator.org/verilator_doc.pdf>`_, and also if possible post on
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the forums the results; there may be additional tweaks possible.)
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Installation & Documentation
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============================
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@ -123,7 +114,7 @@ We appreciate and welcome your contributions in whatever form; please see
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`Contributing to Verilator
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<https://github.com/verilator/verilator/blob/master/docs/CONTRIBUTING.rst>`_.
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Thanks to our `Contributors and Sponsors
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<https://verilator.org/verilator_doc.html#CONTRIBUTORS>`_.
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<https://verilator.org/guide/latest/contributors.html>`_.
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Verilator also supports and encourages commercial support models and
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organizations; please see `Verilator Commercial Support
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@ -154,7 +145,7 @@ Perl Artistic License Version 2.0. See the documentation for more details.
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.. _Icarus Verilog: http://iverilog.icarus.com
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.. _Linux Foundation: https://www.linuxfoundation.org
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.. |Logo| image:: https://www.veripool.org/img/verilator_256_200_min.png
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.. |verilator multithreaded performance bg min| image:: https://www.veripool.org/img/verilator_multithreaded_performance_bg-min.png
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.. |verilator usage 400x200 min| image:: https://www.veripool.org/img/verilator_usage_400x200-min.png
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.. |verilator community 400x125 min| image:: https://www.veripool.org/img/verilator_community_400x125-min.png
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.. |verilator support 400x125 min| image:: https://www.veripool.org/img/verilator_support_400x125-min.png
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.. |verilator multithreaded performance| image:: https://www.veripool.org/img/verilator_multithreaded_performance_bg-min.png
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.. |verilator usage| image:: https://www.veripool.org/img/verilator_usage_400x200-min.png
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.. |verilator community| image:: https://www.veripool.org/img/verilator_community_400x125-min.png
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.. |verilator support| image:: https://www.veripool.org/img/verilator_support_400x125-min.png
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@ -263,8 +263,8 @@ For documentation see L<https://verilator.org/verilator_doc.html>.
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=head1 ARGUMENT SUMMARY
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This is a short summary of the arguments to the "verilator" executable.
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See L<https://verilator.org/verilator_doc.html> for the detailed
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descriptions of these arguments.
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See L<https://verilator.org/guide/latest/exe_verilator.html> for the
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detailed descriptions of these arguments.
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=for VL_SPHINX_EXTRACT "_build/gen/args_verilator.rst"
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@ -432,8 +432,8 @@ descriptions of these arguments.
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This is a short summary of the simulation runtime arguments, i.e. for the
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final Verilated simulation runtime models. See
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L<https://verilator.org/verilator_doc.html> for the detailed description of
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these arguments.
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L<https://verilator.org/guide/latest/exe_verilator.html> for the detailed
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description of these arguments.
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=for VL_SPHINX_EXTRACT "_build/gen/args_verilated.rst"
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@ -160,7 +160,8 @@ verilator_coverage - Verilator coverage analyzer
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Verilator_coverage processes Verilated model-generated coverage reports.
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For documentation see L<https://verilator.org/verilator_doc.html>.
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For documentation see
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L<https://verilator.org/guide/latest/exe_verilator_coverage.html>.
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=head1 ARGUMENT SUMMARY
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@ -199,7 +200,8 @@ C<verilator>, C<lcov>
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L<verilator_coverage --help> which is the source for this document.
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and L<https://verilator.org/verilator_doc.html> for detailed documentation.
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and L<https://verilator.org/guide/latest/exe_verilator_coverage.html> for
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detailed documentation.
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=cut
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@ -539,7 +539,8 @@ Verilator_gantt creates a visual representation to help analyze Verilator
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multithreaded simulation performance, by showing when each macro-task
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starts and ends, and showing when each thread is busy or idle.
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For documentation see L<https://verilator.org/verilator_doc.html>.
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For documentation see
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L<https://verilator.org/guide/latest/exe_verilator_gantt.html>.
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=head1 ARGUMENT SUMMARY
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@ -564,7 +565,8 @@ SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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C<verilator>
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and L<https://verilator.org/verilator_doc.html> for detailed documentation.
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and L<https://verilator.org/guide/latest/exe_verilator_gantt.html> for
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detailed documentation.
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=cut
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@ -214,7 +214,8 @@ the functions are then transformed, assuming the user used Verilator's
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--prof-cfuncs, and a report printed showing the percentage of time, etc,
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in each Verilog block.
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For documentation see L<https://verilator.org/verilator_doc.html>.
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For documentation see
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L<https://verilator.org/guide/latest/exe_verilator_profcfuncs.html>.
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=head1 ARGUMENT SUMMARY
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@ -236,7 +237,8 @@ SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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C<verilator>
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and L<https://verilator.org/verilator_doc.html> for detailed documentation.
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and L<https://verilator.org/guide/latest/exe_verilator_profcfuncs.html> for
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detailed documentation.
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=cut
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