diff --git a/Changes b/Changes index 85d4e1f51..27ef3feac 100644 --- a/Changes +++ b/Changes @@ -3,6 +3,11 @@ Revision history for Verilator The contributors that suggested a given feature are shown in []. [by ...] indicates the contributor was also the author of the fix; Thanks! +* Verilator 3.857 devel + +*** Add --no-trace-params. + + * Verilator 3.856 2014-03-11 *** Support case inside, bug708. [Jan Egil Ruud] diff --git a/bin/verilator b/bin/verilator index 224958ff9..381b3790f 100755 --- a/bin/verilator +++ b/bin/verilator @@ -325,6 +325,7 @@ descriptions in the next sections for more information. --trace-depth Depth of tracing --trace-max-array Maximum bit width for tracing --trace-max-width Maximum array depth for tracing + --trace-params Enable tracing parameters --trace-structs Enable tracing structure names --trace-underscore Enable tracing of _signals -U Undefine preprocessor define @@ -1022,6 +1023,10 @@ Rarely needed. Specify the maximum bit width of a signal that may be traced. Defaults to 256, as tracing large vectors may greatly slow traced simulations. +=item --no-trace-params + +Disable tracing of parameters. + =item --trace-structs Enable tracing to show the name of packed structure, union, and packed diff --git a/src/V3Options.cpp b/src/V3Options.cpp index f34d661cb..316deea69 100644 --- a/src/V3Options.cpp +++ b/src/V3Options.cpp @@ -756,6 +756,7 @@ void V3Options::parseOptsList(FileLine* fl, const string& optdir, int argc, char else if ( !strcmp (sw, "-sv") ) { m_defaultLanguage = V3LangCode::L1800_2005; } else if ( onoff (sw, "-trace", flag/*ref*/) ) { m_trace = flag; } else if ( onoff (sw, "-trace-dups", flag/*ref*/) ) { m_traceDups = flag; } + else if ( onoff (sw, "-trace-params", flag/*ref*/) ) { m_traceParams = flag; } else if ( onoff (sw, "-trace-structs", flag/*ref*/) ) { m_traceStructs = flag; } else if ( onoff (sw, "-trace-underscore", flag/*ref*/) ) { m_traceUnderscore = flag; } else if ( onoff (sw, "-underline-zero", flag/*ref*/) ) { m_underlineZero = flag; } // Undocumented, old Verilator-2 @@ -1223,6 +1224,7 @@ V3Options::V3Options() { m_systemPerl = false; m_trace = false; m_traceDups = false; + m_traceParams = true; m_traceStructs = false; m_traceUnderscore = false; m_underlineZero = false; diff --git a/src/V3Options.h b/src/V3Options.h index ae8637268..45e8cf754 100644 --- a/src/V3Options.h +++ b/src/V3Options.h @@ -90,6 +90,7 @@ class V3Options { bool m_stats; // main switch: --stats bool m_trace; // main switch: --trace bool m_traceDups; // main switch: --trace-dups + bool m_traceParams; // main switch: --trace-params bool m_traceStructs; // main switch: --trace-structs bool m_traceUnderscore;// main switch: --trace-underscore bool m_underlineZero;// main switch: --underline-zero; undocumented old Verilator 2 @@ -215,6 +216,7 @@ class V3Options { bool exe() const { return m_exe; } bool trace() const { return m_trace; } bool traceDups() const { return m_traceDups; } + bool traceParams() const { return m_traceParams; } bool traceStructs() const { return m_traceStructs; } bool traceUnderscore() const { return m_traceUnderscore; } bool orderClockDly() const { return m_orderClockDly; } diff --git a/src/V3TraceDecl.cpp b/src/V3TraceDecl.cpp index 95018c642..825705267 100644 --- a/src/V3TraceDecl.cpp +++ b/src/V3TraceDecl.cpp @@ -261,7 +261,6 @@ private: AstNode* oldValuep = m_traValuep; { m_traShowname += string(" ")+itemp->prettyName(); - m_traValuep->dumpTree(cout, "-tv: "); if (nodep->castStructDType()) { m_traValuep = new AstSel(nodep->fileline(), m_traValuep->cloneTree(true), itemp->lsb(), subtypep->width()); diff --git a/src/verilog.y b/src/verilog.y index c3845f1d3..5722f1882 100644 --- a/src/verilog.y +++ b/src/verilog.y @@ -3728,6 +3728,7 @@ AstVar* V3ParseGrammar::createVariable(FileLine* fileline, string name, AstRange // // Propagate from current module tracing state if (nodep->isGenVar()) nodep->trace(false); + else if (nodep->isParam() && !v3Global.opt.traceParams()) nodep->trace(false); else nodep->trace(v3Global.opt.trace() && nodep->fileline()->tracingOn()); // Remember the last variable created, so we can attach attributes to it in later parsing diff --git a/test_regress/t/t_trace_complex.out b/test_regress/t/t_trace_complex.out index afdfce9e2..5d5d4f519 100644 --- a/test_regress/t/t_trace_complex.out +++ b/test_regress/t/t_trace_complex.out @@ -1,5 +1,5 @@ $version Generated by VerilatedVcd $end -$date Sat Mar 8 15:28:02 2014 +$date Thu Mar 13 20:06:49 2014 $end $timescale 1ns $end @@ -25,10 +25,10 @@ $timescale 1ns $end $var wire 4 % v_strp_strp [3:0] $end $var wire 2 & v_unip_strp [1:0] $end $scope module p2 $end - $var wire 32 7 P [31:0] $end + $var wire 32 7 PARAM [31:0] $end $upscope $end $scope module p3 $end - $var wire 32 8 P [31:0] $end + $var wire 32 8 PARAM [31:0] $end $upscope $end $scope module unnamedblk1 $end $var wire 32 . b [31:0] $end diff --git a/test_regress/t/t_trace_complex.v b/test_regress/t/t_trace_complex.v index 9a3d7a794..e00bc9ad7 100644 --- a/test_regress/t/t_trace_complex.v +++ b/test_regress/t/t_trace_complex.v @@ -43,8 +43,8 @@ module t (clk); arru_arrp_t v_arru_arrp; arru_strp_t v_arru_strp; - p #(.P(2)) p2 (); - p #(.P(3)) p3 (); + p #(.PARAM(2)) p2 (); + p #(.PARAM(3)) p3 (); always @ (posedge clk) begin cyc <= cyc + 1; @@ -70,5 +70,5 @@ module t (clk); endmodule module p; - parameter P = 1; + parameter PARAM = 1; endmodule diff --git a/test_regress/t/t_trace_complex_params.out b/test_regress/t/t_trace_complex_params.out new file mode 100644 index 000000000..fda4a88c0 --- /dev/null +++ b/test_regress/t/t_trace_complex_params.out @@ -0,0 +1,156 @@ +$version Generated by VerilatedVcd $end +$date Thu Mar 13 20:06:34 2014 + $end +$timescale 1ns $end + + $scope module top $end + $var wire 1 0 clk $end + $scope module v $end + $var wire 1 0 clk $end + $var wire 32 # cyc [31:0] $end + $var wire 2 ' v_arrp [2:1] $end + $var wire 2 ( v_arrp_arrp [2:1] $end + $var wire 2 ) v_arrp_strp [1:0] $end + $var wire 1 1 v_arru(1) $end + $var wire 1 2 v_arru(2) $end + $var wire 2 * v_arru_arrp(3) [2:1] $end + $var wire 2 + v_arru_arrp(4) [2:1] $end + $var wire 1 3 v_arru_arru(3)(1) $end + $var wire 1 4 v_arru_arru(3)(2) $end + $var wire 1 5 v_arru_arru(4)(1) $end + $var wire 1 6 v_arru_arru(4)(2) $end + $var wire 2 , v_arru_strp(3) [1:0] $end + $var wire 2 - v_arru_strp(4) [1:0] $end + $var wire 2 $ v_strp [1:0] $end + $var wire 4 % v_strp_strp [3:0] $end + $var wire 2 & v_unip_strp [1:0] $end + $scope module p2 $end + $var wire 32 7 PARAM [31:0] $end + $upscope $end + $scope module p3 $end + $var wire 32 8 PARAM [31:0] $end + $upscope $end + $scope module unnamedblk1 $end + $var wire 32 . b [31:0] $end + $scope module unnamedblk2 $end + $var wire 32 / a [31:0] $end + $upscope $end + $upscope $end + $upscope $end + $upscope $end +$enddefinitions $end + + +#0 +b00000000000000000000000000000000 # +b00 $ +b0000 % +b00 & +b00 ' +b0000 ( +b0000 ) +b00 * +b00 + +b00 , +b00 - +b00000000000000000000000000000000 . +b00000000000000000000000000000000 / +00 +01 +02 +03 +04 +05 +06 +b00000000000000000000000000000010 7 +b00000000000000000000000000000011 8 +#10 +b00000000000000000000000000000001 # +b11 $ +b1111 % +b11 & +b11 ' +b1111 ( +b1111 ) +b11 * +b11 + +b11 , +b11 - +b00000000000000000000000000000101 . +b00000000000000000000000000000101 / +10 +#15 +00 +#20 +b00000000000000000000000000000010 # +b00 $ +b0000 % +b00 & +b00 ' +b0000 ( +b0000 ) +b00 * +b00 + +b00 , +b00 - +10 +#25 +00 +#30 +b00000000000000000000000000000011 # +b11 $ +b1111 % +b11 & +b11 ' +b1111 ( +b1111 ) +b11 * +b11 + +b11 , +b11 - +10 +#35 +00 +#40 +b00000000000000000000000000000100 # +b00 $ +b0000 % +b00 & +b00 ' +b0000 ( +b0000 ) +b00 * +b00 + +b00 , +b00 - +10 +#45 +00 +#50 +b00000000000000000000000000000101 # +b11 $ +b1111 % +b11 & +b11 ' +b1111 ( +b1111 ) +b11 * +b11 + +b11 , +b11 - +10 +#55 +00 +#60 +b00000000000000000000000000000110 # +b00 $ +b0000 % +b00 & +b00 ' +b0000 ( +b0000 ) +b00 * +b00 + +b00 , +b00 - +10 diff --git a/test_regress/t/t_trace_complex_params.pl b/test_regress/t/t_trace_complex_params.pl new file mode 100755 index 000000000..5979d34ff --- /dev/null +++ b/test_regress/t/t_trace_complex_params.pl @@ -0,0 +1,25 @@ +#!/usr/bin/perl +if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2003-2009 by Wilson Snyder. This program is free software; you can +# redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. + +top_filename("t_trace_complex.v"); + +compile ( + verilator_flags2 => ['--cc --trace --no-trace-structs --trace-params'], + ); + +execute ( + check_finished=>1, + ); + +file_grep ("$Self->{obj_dir}/simx.vcd", qr/ PARAM /); + +vcd_identical ("$Self->{obj_dir}/simx.vcd", "t/$Self->{name}.out"); + +ok(1); +1; diff --git a/test_regress/t/t_trace_complex_structs.out b/test_regress/t/t_trace_complex_structs.out index c25972d47..cfcb0a5a9 100644 --- a/test_regress/t/t_trace_complex_structs.out +++ b/test_regress/t/t_trace_complex_structs.out @@ -1,5 +1,5 @@ $version Generated by VerilatedVcd $end -$date Sat Mar 8 15:28:22 2014 +$date Thu Mar 13 20:04:29 2014 $end $timescale 1ns $end @@ -19,12 +19,6 @@ $timescale 1ns $end $var wire 1 ? v_arru_arru(3)(2) $end $var wire 1 @ v_arru_arru(4)(1) $end $var wire 1 A v_arru_arru(4)(2) $end - $scope module p2 $end - $var wire 32 B P [31:0] $end - $upscope $end - $scope module p3 $end - $var wire 32 C P [31:0] $end - $upscope $end $scope module unnamedblk1 $end $var wire 32 9 b [31:0] $end $scope module unnamedblk2 $end @@ -108,8 +102,6 @@ b00000000000000000000000000000000 : 0? 0@ 0A -b00000000000000000000000000000010 B -b00000000000000000000000000000011 C #10 b00000000000000000000000000000001 # 1$ diff --git a/test_regress/t/t_trace_complex_structs.pl b/test_regress/t/t_trace_complex_structs.pl index 1d374806d..cf1ca30c9 100755 --- a/test_regress/t/t_trace_complex_structs.pl +++ b/test_regress/t/t_trace_complex_structs.pl @@ -10,7 +10,7 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); di top_filename("t_trace_complex.v"); compile ( - verilator_flags2 => ['--cc --trace --trace-structs'], + verilator_flags2 => ['--cc --trace --trace-structs --no-trace-params'], ); execute (