forked from github/verilator
Fix range inheritance on port without data type (#2753).
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Wilson Snyder
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a886f28c85
commit
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Changes
2
Changes
@ -9,6 +9,8 @@ The contributors that suggested a given feature are shown in []. Thanks!
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**** Fix little endian interface pin swizzling (#2475). [Don Owen]
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**** Fix range inheritance on port without data type (#2753). [Embedded Go]
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**** Fix TIMESCALE warnings on primitives (#2763). [Xuanqi]
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**** Fix $fread extra semicolon inside statements. [Leendert van Doorn]
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@ -1380,9 +1380,9 @@ portDirNetE: // IEEE: part of port, optional net type and/or direction
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/* empty */ { }
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// // Per spec, if direction given default the nettype.
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// // The higher level rule may override this VARDTYPE with one later in the parse.
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| port_direction { VARDECL(PORT); VARDTYPE_NDECL(nullptr/*default_nettype*/); }
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| port_direction { VARDECL(PORT); } net_type { VARDTYPE_NDECL(nullptr/*default_nettype*/); } // net_type calls VARDECL
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| net_type { } // net_type calls VARDECL
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| port_direction { VARDECL(PORT); VARDTYPE_NDECL(nullptr); }
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| port_direction { VARDECL(PORT); } net_type { VARDTYPE_NDECL(nullptr); } // net_type calls VARDECL
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| net_type { VARDTYPE_NDECL(nullptr); } // net_type calls VARDECL
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;
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port_declNetE: // IEEE: part of port_declaration, optional net type
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129
test_regress/t/t_var_port_xml.out
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129
test_regress/t/t_var_port_xml.out
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@ -0,0 +1,129 @@
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<?xml version="1.0" ?>
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<!-- DESCRIPTION: Verilator output: XML representation of netlist -->
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<verilator_xml>
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<files>
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<file id="a" filename="<built-in>" language="1800-2017"/>
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<file id="b" filename="<command-line>" language="1800-2017"/>
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<file id="c" filename="input.vc" language="1800-2017"/>
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<file id="d" filename="t/t_var_port_xml.v" language="1800-2017"/>
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</files>
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<module_files>
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<file id="d" filename="t/t_var_port_xml.v" language="1800-2017"/>
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</module_files>
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<cells>
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<cell fl="d18" loc="d,18,8,18,11" name="mh2" submodname="mh2" hier="mh2"/>
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</cells>
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<cells>
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<cell fl="d24" loc="d,24,8,24,11" name="mh5" submodname="mh5" hier="mh5"/>
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</cells>
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<cells>
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<cell fl="d26" loc="d,26,8,26,11" name="mh6" submodname="mh6" hier="mh6"/>
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</cells>
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<cells>
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<cell fl="d28" loc="d,28,8,28,11" name="mh7" submodname="mh7" hier="mh7"/>
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</cells>
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<cells>
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<cell fl="d30" loc="d,30,8,30,11" name="mh8" submodname="mh8" hier="mh8"/>
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</cells>
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<cells>
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<cell fl="d32" loc="d,32,8,32,11" name="mh9" submodname="mh9" hier="mh9"/>
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</cells>
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<cells>
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<cell fl="d34" loc="d,34,8,34,12" name="mh10" submodname="mh10" hier="mh10"/>
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</cells>
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<cells>
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<cell fl="d36" loc="d,36,8,36,12" name="mh11" submodname="mh11" hier="mh11"/>
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</cells>
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<cells>
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<cell fl="d38" loc="d,38,8,38,12" name="mh12" submodname="mh12" hier="mh12"/>
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</cells>
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<cells>
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<cell fl="d40" loc="d,40,8,40,12" name="mh13" submodname="mh13" hier="mh13"/>
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</cells>
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<cells>
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<cell fl="d50" loc="d,50,8,50,12" name="mh17" submodname="mh17" hier="mh17"/>
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</cells>
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<cells>
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<cell fl="d52" loc="d,52,8,52,12" name="mh18" submodname="mh18" hier="mh18"/>
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</cells>
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<cells>
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<cell fl="d54" loc="d,54,8,54,12" name="mh19" submodname="mh19" hier="mh19"/>
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</cells>
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<cells>
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<cell fl="d56" loc="d,56,8,56,12" name="mh20" submodname="mh20" hier="mh20"/>
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</cells>
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<cells>
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<cell fl="d58" loc="d,58,8,58,12" name="mh21" submodname="mh21" hier="mh21"/>
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</cells>
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<netlist>
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<module fl="d18" loc="d,18,8,18,11" name="mh2" origName="mh2">
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<var fl="d18" loc="d,18,27,18,47" name="x_inout_wire_integer" dtype_id="1" dir="inout" vartype="integer" origName="x_inout_wire_integer"/>
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</module>
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<module fl="d24" loc="d,24,8,24,11" name="mh5" origName="mh5">
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<var fl="d24" loc="d,24,19,24,37" name="x_input_wire_logic" dtype_id="2" dir="input" vartype="logic" origName="x_input_wire_logic"/>
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</module>
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<module fl="d26" loc="d,26,8,26,11" name="mh6" origName="mh6">
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<var fl="d26" loc="d,26,23,26,40" name="x_input_var_logic" dtype_id="2" dir="input" vartype="logic" origName="x_input_var_logic"/>
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</module>
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<module fl="d28" loc="d,28,8,28,11" name="mh7" origName="mh7">
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<var fl="d28" loc="d,28,31,28,50" name="x_input_var_integer" dtype_id="1" dir="input" vartype="integer" origName="x_input_var_integer"/>
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</module>
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<module fl="d30" loc="d,30,8,30,11" name="mh8" origName="mh8">
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<var fl="d30" loc="d,30,20,30,39" name="x_output_wire_logic" dtype_id="2" dir="output" vartype="logic" origName="x_output_wire_logic"/>
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</module>
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<module fl="d32" loc="d,32,8,32,11" name="mh9" origName="mh9">
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<var fl="d32" loc="d,32,24,32,42" name="x_output_var_logic" dtype_id="2" dir="output" vartype="logic" origName="x_output_var_logic"/>
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</module>
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<module fl="d34" loc="d,34,8,34,12" name="mh10" origName="mh10">
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<var fl="d34" loc="d,34,33,34,62" name="x_output_wire_logic_signed_p6" dtype_id="3" dir="output" vartype="logic" origName="x_output_wire_logic_signed_p6"/>
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</module>
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<module fl="d36" loc="d,36,8,36,12" name="mh11" origName="mh11">
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<var fl="d36" loc="d,36,28,36,48" name="x_output_var_integer" dtype_id="1" dir="output" vartype="integer" origName="x_output_var_integer"/>
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</module>
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<module fl="d38" loc="d,38,8,38,12" name="mh12" origName="mh12">
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<var fl="d38" loc="d,38,23,38,37" name="x_ref_logic_p6" dtype_id="4" dir="ref" vartype="logic" origName="x_ref_logic_p6"/>
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</module>
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<module fl="d40" loc="d,40,8,40,12" name="mh13" origName="mh13">
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<var fl="d40" loc="d,40,17,40,35" name="x_ref_var_logic_u6" dtype_id="5" dir="ref" vartype="port" origName="x_ref_var_logic_u6"/>
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</module>
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<module fl="d50" loc="d,50,8,50,12" name="mh17" origName="mh17">
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<var fl="d50" loc="d,50,31,50,50" name="x_input_var_integer" dtype_id="1" dir="input" vartype="integer" origName="x_input_var_integer"/>
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<var fl="d50" loc="d,50,57,50,75" name="y_input_wire_logic" dtype_id="2" dir="input" vartype="logic" origName="y_input_wire_logic"/>
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</module>
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<module fl="d52" loc="d,52,8,52,12" name="mh18" origName="mh18">
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<var fl="d52" loc="d,52,24,52,42" name="x_output_var_logic" dtype_id="2" dir="output" vartype="logic" origName="x_output_var_logic"/>
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<var fl="d52" loc="d,52,50,52,68" name="y_input_wire_logic" dtype_id="2" dir="input" vartype="logic" origName="y_input_wire_logic"/>
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</module>
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<module fl="d54" loc="d,54,8,54,12" name="mh19" origName="mh19">
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<var fl="d54" loc="d,54,33,54,62" name="x_output_wire_logic_signed_p6" dtype_id="3" dir="output" vartype="logic" origName="x_output_wire_logic_signed_p6"/>
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<var fl="d54" loc="d,54,72,54,92" name="y_output_var_integer" dtype_id="1" dir="output" vartype="integer" origName="y_output_var_integer"/>
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</module>
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<module fl="d56" loc="d,56,8,56,12" name="mh20" origName="mh20">
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<var fl="d56" loc="d,56,23,56,41" name="x_ref_var_logic_p6" dtype_id="4" dir="ref" vartype="logic" origName="x_ref_var_logic_p6"/>
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<var fl="d56" loc="d,56,43,56,61" name="y_ref_var_logic_p6" dtype_id="4" dir="ref" vartype="logic" origName="y_ref_var_logic_p6"/>
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</module>
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<module fl="d58" loc="d,58,8,58,12" name="mh21" origName="mh21">
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<var fl="d58" loc="d,58,17,58,33" name="ref_var_logic_u6" dtype_id="6" dir="ref" vartype="port" origName="ref_var_logic_u6"/>
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<var fl="d58" loc="d,58,41,58,56" name="y_ref_var_logic" dtype_id="2" dir="ref" vartype="logic" origName="y_ref_var_logic"/>
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</module>
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<typetable fl="a0" loc="a,0,0,0,0">
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<unpackarraydtype fl="d58" loc="d,58,34,58,35" id="6" sub_dtype_id="2">
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<range fl="d58" loc="d,58,34,58,35">
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<const fl="d58" loc="d,58,35,58,36" name="32'sh5" dtype_id="7"/>
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<const fl="d58" loc="d,58,37,58,38" name="32'sh0" dtype_id="7"/>
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</range>
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</unpackarraydtype>
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<basicdtype fl="d58" loc="d,58,41,58,56" id="2" name="logic"/>
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<unpackarraydtype fl="d40" loc="d,40,36,40,37" id="5" sub_dtype_id="2">
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<range fl="d40" loc="d,40,36,40,37">
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<const fl="d40" loc="d,40,37,40,38" name="32'sh5" dtype_id="7"/>
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<const fl="d40" loc="d,40,39,40,40" name="32'sh0" dtype_id="7"/>
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</range>
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</unpackarraydtype>
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<basicdtype fl="d38" loc="d,38,17,38,18" id="4" name="logic" left="5" right="0"/>
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<basicdtype fl="d34" loc="d,34,27,34,28" id="3" name="logic" left="5" right="0"/>
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<basicdtype fl="d18" loc="d,18,19,18,26" id="1" name="integer" left="31" right="0"/>
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<basicdtype fl="d40" loc="d,40,37,40,38" id="7" name="logic" left="31" right="0"/>
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</typetable>
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</netlist>
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</verilator_xml>
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25
test_regress/t/t_var_port_xml.pl
Executable file
25
test_regress/t/t_var_port_xml.pl
Executable file
@ -0,0 +1,25 @@
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#!/usr/bin/env perl
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if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
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# DESCRIPTION: Verilator: Verilog Test driver/expect definition
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#
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# Copyright 2012 by Wilson Snyder. This program is free software; you
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# can redistribute it and/or modify it under the terms of either the GNU
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# Lesser General Public License Version 3 or the Perl Artistic License
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# Version 2.0.
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# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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scenarios(vlt => 1);
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my $out_filename = "$Self->{obj_dir}/V$Self->{name}.xml";
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compile(
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verilator_flags2 => ['--xml-only'],
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verilator_make_gmake => 0,
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make_top_shell => 0,
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make_main => 0,
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);
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files_identical($out_filename, $Self->{golden_filename});
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ok(1);
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1;
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59
test_regress/t/t_var_port_xml.v
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59
test_regress/t/t_var_port_xml.v
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@ -0,0 +1,59 @@
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2021 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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// This checks IEEE ports work correctly, we use XML output to make it easy to
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// see all attributes are propagated
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// verilator lint_off MULTITOP
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`ifndef VERILATOR
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module mh0 (wire x_inout_wire_logic);
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endmodule
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module mh1 (integer x_inout_wire_integer);
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endmodule
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`endif
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module mh2 (inout integer x_inout_wire_integer);
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endmodule
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`ifndef VERILATOR
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module mh3 ([5:0] x_inout_wire_logic_p6);
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endmodule
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`endif
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module mh5 (input x_input_wire_logic);
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endmodule
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module mh6 (input var x_input_var_logic);
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endmodule
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module mh7 (input var integer x_input_var_integer);
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endmodule
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module mh8 (output x_output_wire_logic);
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endmodule
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module mh9 (output var x_output_var_logic);
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endmodule
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module mh10(output signed [5:0] x_output_wire_logic_signed_p6);
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endmodule
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module mh11(output integer x_output_var_integer);
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endmodule
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module mh12(ref [5:0] x_ref_logic_p6);
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endmodule
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module mh13(ref x_ref_var_logic_u6 [5:0]);
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endmodule
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`ifndef VERILATOR
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module mh14(wire x_inout_wire_logic, y_inout_wire_logic_p8 [7:0]);
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endmodule
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module mh15(integer x_inout_wire_integer, signed [5:0] y_inout_wire_logic_signed6);
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endmodule
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module mh16([5:0] x_inout_wire_logic_p6, wire y_inout_wire_logic);
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endmodule
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`endif
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module mh17(input var integer x_input_var_integer, wire y_input_wire_logic);
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endmodule
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module mh18(output var x_output_var_logic, input y_input_wire_logic);
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endmodule
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module mh19(output signed [5:0] x_output_wire_logic_signed_p6, integer y_output_var_integer);
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endmodule
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module mh20(ref [5:0] x_ref_var_logic_p6, y_ref_var_logic_p6);
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endmodule
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module mh21(ref ref_var_logic_u6 [5:0], y_ref_var_logic);
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endmodule
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