forked from github/verilator
Tests: Honor make_top_shell=>0 (#2847).
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e9c7f40bb4
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c8d8e95d52
@ -969,9 +969,9 @@ sub compile {
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compile_vlt_cmd(%param);
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if (!$self->{make_top_shell}) {
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if (!$param{make_top_shell}) {
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$param{top_shell_filename}
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= $self->{top_shell_filename} = $self->{top_filename};
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= $self->{top_shell_filename} = "";
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} else {
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$param{top_shell_filename}
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= $self->{top_shell_filename} = "$self->{obj_dir}/$self->{VM_PREFIX}__top.".$self->v_suffix;
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@ -979,7 +979,7 @@ sub compile {
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if ($param{atsim}) {
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$param{tool_define} ||= $param{atsim_define};
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$self->_make_top();
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$self->_make_top() if $param{make_top_shell};
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$self->_run(logfile=>"$self->{obj_dir}/atsim_compile.log",
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fails=>$param{fails},
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cmd=>[($ENV{VERILATOR_ATSIM}||"atsim"),
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@ -995,7 +995,7 @@ sub compile {
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elsif ($param{ghdl}) {
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$param{tool_define} ||= $param{ghdl_define};
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mkdir $self->{ghdl_work_dir};
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$self->_make_top();
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$self->_make_top() if $param{make_top_shell};
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$self->_run(logfile=>"$self->{obj_dir}/ghdl_compile.log",
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fails=>$param{fails},
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cmd=>[($ENV{VERILATOR_GHDL}||"ghdl"),
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@ -1013,7 +1013,7 @@ sub compile {
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}
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elsif ($param{vcs}) {
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$param{tool_define} ||= $param{vcs_define};
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$self->_make_top();
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$self->_make_top() if $param{make_top_shell};
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$self->_run(logfile=>"$self->{obj_dir}/vcs_compile.log",
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fails=>$param{fails},
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cmd=>[($ENV{VERILATOR_VCS}||"vcs"),
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@ -1029,7 +1029,7 @@ sub compile {
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}
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elsif ($param{nc}) {
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$param{tool_define} ||= $param{nc_define};
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$self->_make_top();
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$self->_make_top() if $param{make_top_shell};
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my @more_args;
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if ($self->vhdl) {
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((my $ts = $param{top_shell_filename}) =~ s!\.v!!);
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@ -1051,7 +1051,7 @@ sub compile {
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}
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elsif ($param{ms}) {
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$param{tool_define} ||= $param{ms_define};
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$self->_make_top();
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$self->_make_top() if $param{make_top_shell};
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$self->_run(logfile=>"$self->{obj_dir}/ms_compile.log",
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fails=>$param{fails},
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cmd=>[("vlib $self->{obj_dir}/work && "),
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@ -1067,7 +1067,7 @@ sub compile {
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}
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elsif ($param{iv}) {
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$param{tool_define} ||= $param{iv_define};
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$self->_make_top();
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$self->_make_top() if $param{make_top_shell};
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my @cmd = (($ENV{VERILATOR_IVERILOG}||"iverilog"),
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@{$param{iv_flags}},
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@{$param{iv_flags2}},
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@ -1084,7 +1084,7 @@ sub compile {
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}
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elsif ($param{xsim}) {
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$param{tool_define} ||= $param{xsim_define};
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$self->_make_top();
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$self->_make_top() if $param{make_top_shell};
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$self->_run(logfile=>"$self->{obj_dir}/xsim_compile.log",
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fails=>$param{fails},
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cmd=>[($ENV{VERILATOR_XVLOG}||"xvlog"),
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