Fix size casts as second argument of cast item, bug950.

Changes

@@ -27,6 +27,8 @@ indicates the contributor was also the author of the fix; Thanks!
 
 ****  Fix parameters with function parameter arguments, bug952. [Jie Xu]
 
+****  Fix size casts as second argument of cast item, bug950. [Jonathon Donaldson]
+
 
 * Verilator 3.874 2015-06-06
 

src/V3AstNodes.h

@@ -3514,6 +3514,7 @@ public:
 	setOp1p(lhsp); setOp2p(rhsp);
     }
     ASTNODE_NODE_FUNCS(CastSize, CASTSIZE)
+    // No hasDType because widthing removes this node before the hasDType check
     virtual string emitVerilog() { return "((%r)'(%l))"; }
     virtual string emitC() { V3ERROR_NA; return ""; }
     virtual bool cleanOut() { V3ERROR_NA; return true;} virtual bool cleanLhs() {return true;}

src/V3Width.cpp

@@ -1825,7 +1825,8 @@ private:
 	// Apply width
         iterateCheck(nodep,"Case expression",nodep->exprp(),CONTEXT,FINAL,subDTypep,EXTEND_LHS);
 	for (AstCaseItem* itemp = nodep->itemsp(); itemp; itemp=itemp->nextp()->castCaseItem()) {
-	    for (AstNode* condp = itemp->condsp(); condp; condp=condp->nextp()) {
+	    for (AstNode* nextcp, *condp = itemp->condsp(); condp; condp=nextcp) {
+		nextcp = condp->nextp(); // Final may cause the node to get replaced
 		iterateCheck(nodep,"Case Item",condp,CONTEXT,FINAL,subDTypep,EXTEND_LHS);
 	    }
 	}

test_regress/t/t_case_group.pl

@@ -0,0 +1,18 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+
+compile (
+    );
+
+execute (
+    check_finished=>1,
+    );
+
+ok(1);
+1;

test_regress/t/t_case_group.v

@@ -0,0 +1,25 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2014 by Jonathon Donaldson.
+
+module t
+  (
+   input 	i_clk,
+   input [6:0] 	i_input,
+   output logic o_output
+   );
+
+   always_ff @(posedge i_clk)
+     // verilator lint_off CASEINCOMPLETE
+     case (i_input)
+       7'(92+2),
+       7'(92+3): o_output <= 1'b1;
+     endcase
+
+   initial begin
+      $write("*-* All Finished *-*\n");
+      $finish;
+   end
+
+endmodule