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Fix parsing "output signed" in V2K port list, msg2540.

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Wilson Snyder 2018-03-29 20:10:27 -04:00
parent e3354a0191
commit c7c99d8553
4 changed files with 73 additions and 0 deletions
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@ -4,6 +4,8 @@ The contributors that suggested a given feature are shown in []. Thanks!
* Verilator 3.923 devel
**** Fix parsing "output signed" in V2K port list, msg2540. [James Jung]
* Verilator 3.922 2018-03-17

2
src/verilog.y
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@ -948,6 +948,8 @@ port<nodep>: // ==IEEE: port
{ $$=$4; VARDTYPE($3); $$->addNextNull(VARDONEP($$,$5,$6)); }
| portDirNetE yVAR implicit_typeE portSig variable_dimensionListE sigAttrListE
{ $$=$4; VARDTYPE($3); $$->addNextNull(VARDONEP($$,$5,$6)); }
| portDirNetE signing portSig variable_dimensionListE sigAttrListE
{ $$=$3; VARDTYPE(new AstBasicDType($3->fileline(), LOGIC_IMPLICIT, $2)); $$->addNextNull(VARDONEP($$,$4,$5)); }
| portDirNetE signingE rangeList portSig variable_dimensionListE sigAttrListE
{ $$=$4; VARDTYPE(GRAMMARP->addRange(new AstBasicDType($3->fileline(), LOGIC_IMPLICIT, $2), $3,true)); $$->addNextNull(VARDONEP($$,$5,$6)); }
| portDirNetE /*implicit*/ portSig variable_dimensionListE sigAttrListE

18
test_regress/t/t_inst_signed1.pl Executable file
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@ -0,0 +1,18 @@
#!/usr/bin/perl
if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2003 by Wilson Snyder. This program is free software; you can
# redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
compile (
);
execute (
check_finished=>1,
);
ok(1);
1;

51
test_regress/t/t_inst_signed1.v Normal file
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@ -0,0 +1,51 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2018 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
reg signed i;
wire signed o1;
wire signed o2;
integer cyc; initial cyc=0;
sub1 sub1 (.i(i), .o(o1));
sub2 sub2 (.i(o1), .o(o2));
always @ (posedge clk) begin
cyc <= cyc + 1;
if (cyc==0) begin
i <= 1'b0;
end
else if (cyc==1) begin
if (o2 != 1'b0) $stop;
i <= 1'b1;
end
else if (cyc==2) begin
if (o2 != 1'b1) $stop;
end
if (cyc==3) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
//msg2540
module sub1 (
input signed i,
output signed o);
wire signed o = ~i;
endmodule
module sub2 (i,o);
input signed i;
output signed o;
wire signed o = ~i;
endmodule