diff --git a/Changes b/Changes
index 3dd9088a4..bcbbbb381 100644
--- a/Changes
+++ b/Changes
@@ -21,6 +21,7 @@ Verilator 4.225 devel
 * Fix incorrect tristate logic (#3399) [shareefj, Vighnesh Iyer]
 * Fix segfault exporting non-existant package (#3535).
 * Fix case statement comparing string literal (#3544). [Gustav Svensk]
+* Fix --hierarchical with order-based pin connections (#3583). [Kelin9298]
 * Improve Verilation speed with --threads on large designs. [Geza Lore]
 * Rename trace rolloverSize() (#3570).
 
diff --git a/src/V3VariableOrder.cpp b/src/V3VariableOrder.cpp
index 6dda8290b..d62cfb50f 100644
--- a/src/V3VariableOrder.cpp
+++ b/src/V3VariableOrder.cpp
@@ -156,15 +156,16 @@ class VariableOrder final {
                 auto& attributes = m_attributes(varp);
                 // Stratum
                 const int sigbytes = varp->dtypeSkipRefp()->widthAlignBytes();
-                attributes.stratum = (varp->isUsedClock() && varp->widthMin() == 1)   ? 0
-                                     : VN_IS(varp->dtypeSkipRefp(), UnpackArrayDType) ? 8
-                                     : (varp->basicp() && varp->basicp()->isOpaque()) ? 7
-                                     : (varp->isScBv() || varp->isScBigUint())        ? 6
-                                     : (sigbytes == 8)                                ? 5
-                                     : (sigbytes == 4)                                ? 4
-                                     : (sigbytes == 2)                                ? 2
-                                     : (sigbytes == 1)                                ? 1
-                                                                                      : 9;
+                attributes.stratum = (v3Global.opt.hierChild() && varp->isPrimaryIO()) ? 0
+                                     : (varp->isUsedClock() && varp->widthMin() == 1)  ? 1
+                                     : VN_IS(varp->dtypeSkipRefp(), UnpackArrayDType)  ? 9
+                                     : (varp->basicp() && varp->basicp()->isOpaque())  ? 8
+                                     : (varp->isScBv() || varp->isScBigUint())         ? 7
+                                     : (sigbytes == 8)                                 ? 6
+                                     : (sigbytes == 4)                                 ? 5
+                                     : (sigbytes == 2)                                 ? 3
+                                     : (sigbytes == 1)                                 ? 2
+                                                                                       : 10;
                 // Anonymous structure ok
                 attributes.anonOk = EmitCBaseVisitor::isAnonOk(varp);
             }
diff --git a/test_regress/t/t_hier_bynum.pl b/test_regress/t/t_hier_bynum.pl
new file mode 100755
index 000000000..2c0fb4904
--- /dev/null
+++ b/test_regress/t/t_hier_bynum.pl
@@ -0,0 +1,19 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+
+scenarios(vlt_all => 1);
+
+compile(
+    v_flags2 => ['t/t_hier_block.cpp'],
+    verilator_flags2 => ['--hierarchical'],
+    verilator_make_gmake => 0,
+    );
+
+ok(1);
+1;
diff --git a/test_regress/t/t_hier_bynum.v b/test_regress/t/t_hier_bynum.v
new file mode 100644
index 000000000..4f930143d
--- /dev/null
+++ b/test_regress/t/t_hier_bynum.v
@@ -0,0 +1,29 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2022 by Wilson Snyder.
+
+module flop (
+             output reg q,
+             input wire d,
+             input wire clk
+             );
+
+   // verilator hier_block
+
+   always_ff @(posedge clk) begin
+     q <= d;
+   end
+
+endmodule
+
+module t (
+          output wire q,
+          input wire  d,
+          input wire  clk
+          );
+
+   // This intentionally uses pin number ordering
+   flop u_flop(q, d, clk);
+
+endmodule