From c28a6eef3bfeb8b1cbea262cf8a5ecddc341e8d0 Mon Sep 17 00:00:00 2001
From: Wilson Snyder <wsnyder@wsnyder.org>
Date: Mon, 11 Sep 2017 19:18:58 -0400
Subject: [PATCH] Fix whitespace issues, bug1203.

---
 README.pod                               |  2 +-
 TODO                                     |  2 +-
 configure.ac                             |  1 +
 include/verilated.cpp                    |  2 +-
 include/verilated_save.cpp               |  2 +-
 include/verilated_syms.h                 |  2 +-
 install-sh                               | 14 ++---
 internals.pod                            |  2 +-
 src/V3Active.cpp                         |  2 +-
 src/V3Assert.cpp                         | 10 +--
 src/V3AstNodes.h                         |  2 +-
 src/V3Changed.cpp                        |  6 +-
 src/V3EmitC.cpp                          |  2 +-
 src/V3Gate.cpp                           |  6 +-
 src/V3Number.cpp                         |  2 +-
 src/V3Options.h                          |  2 +-
 src/V3Order.cpp                          |  4 +-
 src/V3Os.cpp                             |  2 +-
 src/V3PreProc.cpp                        |  6 +-
 src/V3Scope.cpp                          |  4 +-
 src/V3Width.cpp                          |  6 +-
 src/VlcMain.cpp                          |  2 +-
 src/VlcOptions.h                         |  2 +-
 src/VlcTop.cpp                           |  2 +-
 src/verilog.y                            |  2 +-
 test_regress/t/t_array_packed_sysfunct.v |  4 +-
 test_regress/t/t_array_query.v           |  6 +-
 test_regress/t/t_assert_cover.v          | 10 +--
 test_regress/t/t_assign_inline.v         | 12 ++--
 test_regress/t/t_bench_mux4k.v           |  8 +--
 test_regress/t/t_bench_synmul.pl         |  2 +-
 test_regress/t/t_case_dupitems.v         |  2 +-
 test_regress/t/t_case_huge_sub3.v        |  2 +-
 test_regress/t/t_case_reducer.v          | 10 +--
 test_regress/t/t_cellarray.v             |  4 +-
 test_regress/t/t_clk_2in.pl              |  2 +-
 test_regress/t/t_clk_concat6.v           |  2 +-
 test_regress/t/t_clocker.v               |  4 +-
 test_regress/t/t_concat_opt.v            |  2 +-
 test_regress/t/t_const_overflow_bad.v    |  2 +-
 test_regress/t/t_cover_sva_notflat.v     |  2 +-
 test_regress/t/t_display.pl              |  4 +-
 test_regress/t/t_display.v               |  4 +-
 test_regress/t/t_display_noopt.pl        |  4 +-
 test_regress/t/t_dist_manifest.pl        | 26 +++++---
 test_regress/t/t_dist_whitespace.pl      | 51 ++++++++++++++++
 test_regress/t/t_dpi_context.v           |  2 +-
 test_regress/t/t_dpi_display.pl          | 20 +++---
 test_regress/t/t_dpi_display.v           |  8 +--
 test_regress/t/t_dpi_display_c.cpp       |  2 +-
 test_regress/t/t_dpi_imp_gen.v           |  2 +-
 test_regress/t/t_dpi_shortcircuit2.v     |  2 +-
 test_regress/t/t_dpi_vams.v              |  6 +-
 test_regress/t/t_embed1.pl               |  2 +-
 test_regress/t/t_embed1_c.cpp            |  2 +-
 test_regress/t/t_embed1_child.v          |  2 +-
 test_regress/t/t_embed1_wrap.v           |  4 +-
 test_regress/t/t_enum_large_methods.v    |  6 +-
 test_regress/t/t_enum_type_methods.v     | 50 +++++++--------
 test_regress/t/t_for_init_bug.v          |  2 +-
 test_regress/t/t_func_begin2.v           |  2 +-
 test_regress/t/t_func_const_bad.v        |  2 +-
 test_regress/t/t_func_noinl.v            |  4 +-
 test_regress/t/t_func_wide_out_bad.v     |  4 +-
 test_regress/t/t_gate_unsup.v            |  2 +-
 test_regress/t/t_gen_inc.v               |  2 +-
 test_regress/t/t_gen_missing.v           |  4 +-
 test_regress/t/t_inst_array_partial.v    |  4 +-
 test_regress/t/t_inst_dtree.v            |  2 +-
 test_regress/t/t_inst_signed.v           |  2 +-
 test_regress/t/t_inst_slice.v            |  2 +-
 test_regress/t/t_lint_blksync_bad.v      |  8 +--
 test_regress/t/t_lint_blksync_loop.v     |  2 +-
 test_regress/t/t_lint_inherit.v          |  4 +-
 test_regress/t/t_lint_multidriven_bad.v  |  2 +-
 test_regress/t/t_lint_unsup_deassign.v   |  2 +-
 test_regress/t/t_lint_unsup_mixed.v      |  4 +-
 test_regress/t/t_lint_unused_bad.v       |  2 +-
 test_regress/t/t_math_msvc_64.v          | 26 ++++----
 test_regress/t/t_math_pow5.v             |  2 +-
 test_regress/t/t_math_real.v             |  4 +-
 test_regress/t/t_math_sign_extend.v      | 78 ++++++++++++------------
 test_regress/t/t_mem_multi_io3.v         |  8 +--
 test_regress/t/t_mem_slice_conc_bad.v    |  2 +-
 test_regress/t/t_mem_twoedge.v           |  2 +-
 test_regress/t/t_mod_recurse.v           |  8 +--
 test_regress/t/t_order_multidriven.v     |  2 +-
 test_regress/t/t_order_quad.v            |  2 +-
 test_regress/t/t_package.v               |  2 +-
 test_regress/t/t_package_ddecl.v         |  2 -
 test_regress/t/t_package_verb.v          |  2 +-
 test_regress/t/t_param_mem_attr.v        |  2 +-
 test_regress/t/t_param_value.v           | 10 +--
 test_regress/t/t_param_wide_io.v         |  4 +-
 test_regress/t/t_pp_dupdef_bad.pl        |  4 +-
 test_regress/t/t_savable.v               |  2 +-
 test_regress/t/t_select_index2.v         |  4 +-
 test_regress/t/t_select_lhs_oob.v        |  2 +-
 test_regress/t/t_stream.v                |  2 +-
 test_regress/t/t_struct_pat_width.v      |  2 +-
 test_regress/t/t_struct_port.v           |  6 +-
 test_regress/t/t_sv_conditional.v        | 58 +++++++++---------
 test_regress/t/t_tri_gen.v               |  4 +-
 test_regress/t/t_tri_ifbegin.v           |  2 +-
 test_regress/t/t_tri_pull2_bad.v         |  4 +-
 test_regress/t/t_tri_pull_bad.v          |  2 +-
 test_regress/t/t_typedef_signed.v        |  2 +-
 test_regress/t/t_unopt_bound.v           |  2 +-
 test_regress/t/t_var_assign_landr.v      |  2 +-
 test_regress/t/t_var_in_assign.v         |  2 +-
 test_regress/t/t_var_pinsizes.v          |  1 -
 test_regress/t/t_var_static.v            |  4 +-
 test_regress/t/t_var_tieout.v            |  2 +-
 test_regress/t/t_vpi_var.v               |  2 +-
 test_verilated/vgen.pl                   |  1 +
 115 files changed, 370 insertions(+), 312 deletions(-)
 create mode 100755 test_regress/t/t_dist_whitespace.pl

diff --git a/README.pod b/README.pod
index acf0f15d8..a04ee4b57 100644
--- a/README.pod
+++ b/README.pod
@@ -51,7 +51,7 @@ output (not Verilator itself) compiles under MSVC++ 2008 and newer.
 
 =head1 INSTALLATION
 
-For more details see 
+For more details see
 L<http://www.veripool.org/projects/verilator/wiki/Installing>.
 
 If you will be modifying Verilator, you should use the "git" method as it
diff --git a/TODO b/TODO
index 6c4b4133b..6eb3f3742 100755
--- a/TODO
+++ b/TODO
@@ -41,7 +41,7 @@ Testing:
 	* // verilator debug in code so can see only tree affecting those nodes
 
 Usability:
-	* Detect and pre-remove most UNOPTFLATs (4.000) 
+	* Detect and pre-remove most UNOPTFLATs (4.000)
 	* Better reporting of unopt problems, including what lines of code
 	* Report more errors (all of them?) before exiting [Eugene Weber]
 	* Auto-create scons config files
diff --git a/configure.ac b/configure.ac
index d1ebd0fed..bc97d4c2b 100644
--- a/configure.ac
+++ b/configure.ac
@@ -8,6 +8,7 @@
 #AC_INIT([Verilator],[#.### devel])
 AC_INIT([Verilator],[3.911 devel])
 # When releasing, also update header of Changes file
+# and commit using "devel release" or "Version bump" message
 
 AC_CONFIG_HEADER(src/config_build.h)
 AC_CONFIG_FILES(Makefile src/Makefile src/Makefile_obj include/verilated.mk include/verilated_config.h verilator.pc)
diff --git a/include/verilated.cpp b/include/verilated.cpp
index 997929c2a..77ff0944f 100644
--- a/include/verilated.cpp
+++ b/include/verilated.cpp
@@ -1454,7 +1454,7 @@ void VerilatedScope::varInsert(int finalize, const char* namep, void* datap,
 VerilatedVar* VerilatedScope::varFind(const char* namep) const {
     if (VL_LIKELY(m_varsp)) {
 	VerilatedVarNameMap::iterator it = m_varsp->find(namep);
-	if (VL_LIKELY(it != m_varsp->end())) {	
+	if (VL_LIKELY(it != m_varsp->end())) {
 	    return &(it->second);
 	}
     }
diff --git a/include/verilated_save.cpp b/include/verilated_save.cpp
index 1f30f90e1..09731e74c 100644
--- a/include/verilated_save.cpp
+++ b/include/verilated_save.cpp
@@ -204,7 +204,7 @@ void VerilatedRestore::fill() {
     for (vluint8_t* sp=m_cp; sp < m_endp;) *rp++ = *sp++;  // Overlaps
     m_endp = m_bufp + (m_endp - m_cp);
     m_cp = m_bufp; // Reset buffer
-    // Read into buffer starting at m_endp 
+    // Read into buffer starting at m_endp
     while (1) {
 	ssize_t remaining = (m_bufp+bufferSize() - m_endp);
 	if (remaining==0) break;
diff --git a/include/verilated_syms.h b/include/verilated_syms.h
index 9826f8fda..635da0bdc 100644
--- a/include/verilated_syms.h
+++ b/include/verilated_syms.h
@@ -36,7 +36,7 @@
 /// Verilator range
 
 // See also V3Ast::VNumRange
-class VerilatedRange { 
+class VerilatedRange {
     int		m_left;
     int		m_right;
 protected:
diff --git a/install-sh b/install-sh
index f98503c2a..058b26c82 100644
--- a/install-sh
+++ b/install-sh
@@ -124,7 +124,7 @@ if [ x"$dir_arg" != x ]; then
 else
 
 # Waiting for this to be detected by the "$instcmd $src $dsttmp" command
-# might cause directories to be created, which would be especially bad 
+# might cause directories to be created, which would be especially bad
 # if $src (and thus $dsttmp) contains '*'.
 
 	if [ -f $src -o -d $src ]
@@ -134,7 +134,7 @@ else
 		echo "install:  $src does not exist"
 		exit 1
 	fi
-	
+
 	if [ x"$dst" = x ]
 	then
 		echo "install:	no destination specified"
@@ -162,7 +162,7 @@ dstdir=`echo $dst | sed -e 's,[^/]*$,,;s,/$,,;s,^$,.,'`
 
 # Skip lots of stat calls in the usual case.
 if [ ! -d "$dstdir" ]; then
-defaultIFS='	
+defaultIFS='
 '
 IFS="${IFS-${defaultIFS}}"
 
@@ -201,17 +201,17 @@ else
 
 # If we're going to rename the final executable, determine the name now.
 
-	if [ x"$transformarg" = x ] 
+	if [ x"$transformarg" = x ]
 	then
 		dstfile=`basename $dst`
 	else
-		dstfile=`basename $dst $transformbasename | 
+		dstfile=`basename $dst $transformbasename |
 			sed $transformarg`$transformbasename
 	fi
 
 # don't allow the sed command to completely eliminate the filename
 
-	if [ x"$dstfile" = x ] 
+	if [ x"$dstfile" = x ]
 	then
 		dstfile=`basename $dst`
 	else
@@ -242,7 +242,7 @@ else
 # Now rename the file to the real destination.
 
 	$doit $rmcmd -f $dstdir/$dstfile &&
-	$doit $mvcmd $dsttmp $dstdir/$dstfile 
+	$doit $mvcmd $dsttmp $dstdir/$dstfile
 
 fi &&
 
diff --git a/internals.pod b/internals.pod
index 26f2a8f38..2f4e40172 100644
--- a/internals.pod
+++ b/internals.pod
@@ -709,7 +709,7 @@ Start GDB, then C<start> with the remaining arguments.
   Temporary breakpoint 1, main (argc=13, argv=0xbfffefa4, env=0xbfffefdc)
       at ../Verilator.cpp:615
   615         ios::sync_with_stdio();
-  (gdb) 
+  (gdb)
 
 You can then continue execution with breakpoints as required.
 
diff --git a/src/V3Active.cpp b/src/V3Active.cpp
index 9f44684dd..f5c6810ed 100644
--- a/src/V3Active.cpp
+++ b/src/V3Active.cpp
@@ -176,7 +176,7 @@ private:
 	    if (m_check == CT_INITIAL) {
 		nodep->v3warn(INITIALDLY,"Delayed assignments (<=) in initial or final block; suggest blocking assignments (=).");
 	    } else if (m_check == CT_LATCH) {
-		// Suppress. Shouldn't matter that the interior of the latch races 
+		// Suppress. Shouldn't matter that the interior of the latch races
 	    } else {
 		nodep->v3warn(COMBDLY,"Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).");
 	    }
diff --git a/src/V3Assert.cpp b/src/V3Assert.cpp
index 762b88ff3..481752de0 100644
--- a/src/V3Assert.cpp
+++ b/src/V3Assert.cpp
@@ -162,7 +162,7 @@ private:
 	// Bye
 	pushDeletep(nodep); VL_DANGLING(nodep);
     }
-    
+
     virtual void visit(AstIf* nodep) {
 	if (nodep->user1SetOnce()) return;
 	if (nodep->uniquePragma() || nodep->unique0Pragma()) {
@@ -177,12 +177,12 @@ private:
 
 		// Recurse into the true case.
 		ifp->ifsp()->iterateAndNext(*this);
-		
+
 		// If the last else is not an else if, recurse into that too.
 		if (ifp->elsesp() && !nextifp) {
 		    ifp->elsesp()->iterateAndNext(*this);
 		}
-		
+
 		// Build a bitmask of the true predicates
 	        AstNode* predp = ifp->condp()->cloneTree(false);
 	        if (propp) {
@@ -195,13 +195,13 @@ private:
 		if (ifp->elsesp() && !nextifp) {
 		    hasDefaultElse = true;
 		}
-		
+
 		ifp = nextifp;
 	    } while (ifp);
 
 	    AstNode *newifp = nodep->cloneTree(false);
 	    bool allow_none = nodep->unique0Pragma();
-	    
+
 	    // Note: if this ends with an 'else', then we don't need to validate that one of the
 	    // predicates evaluates to true.
 	    AstNode* ohot = ((allow_none || hasDefaultElse)
diff --git a/src/V3AstNodes.h b/src/V3AstNodes.h
index c93324dd9..0f42a36c9 100644
--- a/src/V3AstNodes.h
+++ b/src/V3AstNodes.h
@@ -254,7 +254,7 @@ public:
 	m_uniqueNum = uniqueNumInc();
     }
     ASTNODE_NODE_FUNCS(DefImplicitDType)
-    virtual bool same(AstNode* samep) const { return m_uniqueNum==samep->castDefImplicitDType()->m_uniqueNum; } 
+    virtual bool same(AstNode* samep) const { return m_uniqueNum==samep->castDefImplicitDType()->m_uniqueNum; }
     virtual bool similarDType(AstNodeDType* samep) const {
 	return type()==samep->type() && same(samep); }
     virtual V3Hash sameHash() const { return V3Hash(m_uniqueNum); }
diff --git a/src/V3Changed.cpp b/src/V3Changed.cpp
index 3c57ec92a..ae714a895 100644
--- a/src/V3Changed.cpp
+++ b/src/V3Changed.cpp
@@ -111,8 +111,8 @@ private:
     AstVarScope*	m_vscp;		// Original (non-change) variable we're change-detecting
     AstVarScope*	m_newvscp;	// New (change detect) variable we're change-detecting
     AstNode*		m_varEqnp;	// Original var's equation to get var value
-    AstNode*		m_newLvEqnp;	// New var's equation to read value 
-    AstNode*		m_newRvEqnp;	// New var's equation to set value 
+    AstNode*		m_newLvEqnp;	// New var's equation to read value
+    AstNode*		m_newRvEqnp;	// New var's equation to set value
     uint32_t		m_detects;	// # detects created
 
     // CONSTANTS
@@ -278,7 +278,7 @@ private:
 	}
     }
     virtual void visit(AstNodeMath* nodep) {
-	// Short-circuit 
+	// Short-circuit
     }
     //--------------------
     // Default: Just iterate
diff --git a/src/V3EmitC.cpp b/src/V3EmitC.cpp
index e6a9c3750..0b9be3402 100644
--- a/src/V3EmitC.cpp
+++ b/src/V3EmitC.cpp
@@ -603,7 +603,7 @@ public:
 	puts(nodep->hiername());
 	puts(nodep->varp()->name());
     }
-    void emitCvtPackStr(AstNode* nodep) { 
+    void emitCvtPackStr(AstNode* nodep) {
 	if (AstConst* constp = nodep->castConst()) {
 	    putbs("string(");
 	    putsQuoted(constp->num().toString());
diff --git a/src/V3Gate.cpp b/src/V3Gate.cpp
index 14d1b12b0..728f50d52 100644
--- a/src/V3Gate.cpp
+++ b/src/V3Gate.cpp
@@ -1133,7 +1133,7 @@ void GateVisitor::dedupe() {
 
 
 //######################################################################
-// Recurse through the graph, try to merge assigns 
+// Recurse through the graph, try to merge assigns
 
 class GateMergeAssignsGraphVisitor : public GateGraphBaseVisitor {
 private:
@@ -1145,7 +1145,7 @@ private:
     V3Double0        m_numMergedAssigns;	// Statistic tracking
 
 
-    // assemble two Sel into one if possible 
+    // assemble two Sel into one if possible
     AstSel* merge(AstSel* pre, AstSel* cur) {
 	AstVarRef* preVarRefp = pre->fromp()->castVarRef();
 	AstVarRef* curVarRefp = cur->fromp()->castVarRef();
@@ -1201,7 +1201,7 @@ private:
 			    // update the graph
 			    {
 				// delete all inedges to lvertexp
-				if (!lvertexp->inEmpty()) { 
+				if (!lvertexp->inEmpty()) {
 				    for (V3GraphEdge* ledgep = lvertexp->inBeginp(); ledgep; ) {
 					V3GraphEdge* oedgep = ledgep;
 					ledgep = ledgep->inNextp();
diff --git a/src/V3Number.cpp b/src/V3Number.cpp
index 8ec864a85..f172e0001 100644
--- a/src/V3Number.cpp
+++ b/src/V3Number.cpp
@@ -446,7 +446,7 @@ bool V3Number::displayedFmtLegal(char format) {
     case 's': return true;
     case 't': return true;
     case 'u': return true; // Packed 2-state
-    case 'v': return true; // Strength 
+    case 'v': return true; // Strength
     case 'x': return true;
     case 'z': return true; // Packed 4-state
     case '@': return true; // Packed string
diff --git a/src/V3Options.h b/src/V3Options.h
index 621d64510..44cf65bde 100644
--- a/src/V3Options.h
+++ b/src/V3Options.h
@@ -145,7 +145,7 @@ class V3Options {
     bool	m_oCombine;	// main switch: -Ob: common icode packing
     bool	m_oConst;	// main switch: -Oc: constant folding
     bool	m_oDedupe;	// main switch: -Od: logic deduplication
-    bool	m_oAssemble;	// main switch: -Om: assign assemble 
+    bool	m_oAssemble;	// main switch: -Om: assign assemble
     bool	m_oExpand;	// main switch: -Ox: expansion of C macros
     bool	m_oFlopGater;	// main switch: -Of: flop gater detection
     bool	m_oGate;	// main switch: -Og: gate wire elimination
diff --git a/src/V3Order.cpp b/src/V3Order.cpp
index 004e92da0..3216bd367 100644
--- a/src/V3Order.cpp
+++ b/src/V3Order.cpp
@@ -242,7 +242,7 @@ struct OrderVarFanoutCmp {
 };
 
 //######################################################################
-// The class is used for propagating the clocker attribute for further 
+// The class is used for propagating the clocker attribute for further
 // avoiding marking clock signals as circular.
 // Transformation:
 //    while (newClockerMarked)
@@ -251,7 +251,7 @@ struct OrderVarFanoutCmp {
 //                mark LHS as clocker as well.
 //                newClockerMarked = true;
 //
-// In addition it also check whether clock and data signals are mixed, and 
+// In addition it also check whether clock and data signals are mixed, and
 // produce a CLKDATA warning if so.
 //
 class OrderClkMarkVisitor : public AstNVisitor {
diff --git a/src/V3Os.cpp b/src/V3Os.cpp
index 9c014d850..d5296213e 100644
--- a/src/V3Os.cpp
+++ b/src/V3Os.cpp
@@ -68,7 +68,7 @@ void V3Os::setenvStr(const string& envvar, const string& value, const string& wh
 }
 
 //######################################################################
-// Generic filename utilities 
+// Generic filename utilities
 
 string V3Os::filenameFromDirBase (const string& dir, const string& basename) {
     // Don't return ./{filename} because if filename was absolute, that makes it relative
diff --git a/src/V3PreProc.cpp b/src/V3PreProc.cpp
index b153a3789..a8342fffd 100644
--- a/src/V3PreProc.cpp
+++ b/src/V3PreProc.cpp
@@ -323,8 +323,10 @@ void V3PreProcImp::define(FileLine* fl, const string& name, const string& value,
     UINFO(4,"DEFINE '"<<name<<"' as '"<<value<<"' params '"<<params<<"'"<<endl);
     if (defExists(name)) {
 	if (!(defValue(name)==value && defParams(name)==params)) {  // Duplicate defs are OK
-	    fl->v3warn(REDEFMACRO,"Redefining existing define: "<<name<<", with different value: "<<value<<" "<<params);
-	    defFileline(name)->v3warn(REDEFMACRO,"Previous definition is here, with value: "<<defValue(name)<<" "<<defParams(name));
+	    fl->v3warn(REDEFMACRO,"Redefining existing define: "<<name<<", with different value: "
+		       <<value<<(params=="" ? "":" ")<<params);
+	    defFileline(name)->v3warn(REDEFMACRO,"Previous definition is here, with value: "
+				      <<defValue(name)<<(defParams(name)=="" ? "":" ")<<defParams(name));
 	}
 	undef(name);
     }
diff --git a/src/V3Scope.cpp b/src/V3Scope.cpp
index b8e3cfe64..f90cefdec 100644
--- a/src/V3Scope.cpp
+++ b/src/V3Scope.cpp
@@ -60,7 +60,7 @@ private:
     // STATE, for passing down one level of hierarchy (may need save/restore)
     AstCell*	m_aboveCellp;	// Cell that instantiates this module
     AstScope*	m_aboveScopep;	// Scope that instantiates this scope
-    
+
     PackageScopeMap	m_packageScopes;	// Scopes for each package
     VarScopeMap		m_varScopes;		// Varscopes created for each scope and var
     VarRefScopeSet	m_varRefScopes;		// Varrefs-in-scopes needing fixup when donw
@@ -265,7 +265,7 @@ private:
 	    // the var's referenced package etc might not be created yet.
 	    // So push to a list and post-correct
 	    m_varRefScopes.insert(make_pair(nodep, m_scopep));
-	} 
+	}
    }
     virtual void visit(AstScopeName* nodep) {
 	// If there's a %m in the display text, we add a special node that will contain the name()
diff --git a/src/V3Width.cpp b/src/V3Width.cpp
index 8eb005a73..84fdc7a95 100644
--- a/src/V3Width.cpp
+++ b/src/V3Width.cpp
@@ -2181,7 +2181,7 @@ private:
 		// TODO Simple dtype checking, should be a more general check
 		AstNodeArrayDType* exprArrayp = exprDTypep->skipRefp()->castUnpackArrayDType();
 		AstNodeArrayDType* modArrayp = modDTypep->skipRefp()->castUnpackArrayDType();
-		if (exprArrayp && modArrayp && exprArrayp->subDTypep()->skipRefp()->castIfaceRefDType() 
+		if (exprArrayp && modArrayp && exprArrayp->subDTypep()->skipRefp()->castIfaceRefDType()
 		    && exprArrayp->declRange().elements() != modArrayp->declRange().elements()) {
 		    int exprSize = exprArrayp->declRange().elements();
 		    int modSize = modArrayp->declRange().elements();
@@ -3555,7 +3555,7 @@ private:
 	}
 	return patmap;
     }
-    
+
 
     //----------------------------------------------------------------------
     // METHODS - special type detection
@@ -3599,7 +3599,7 @@ private:
 	}
 	m_vup = saveVup;
     }
-    void userIterateAndNext(AstNode* nodep, WidthVP* vup) {	
+    void userIterateAndNext(AstNode* nodep, WidthVP* vup) {
 	if (!nodep) return;
 	WidthVP* saveVup = m_vup;
 	{
diff --git a/src/VlcMain.cpp b/src/VlcMain.cpp
index 86629b34a..d02f1821a 100644
--- a/src/VlcMain.cpp
+++ b/src/VlcMain.cpp
@@ -179,7 +179,7 @@ int main(int argc, char** argv, char** env) {
 	    }
         }
     }
-    
+
     // Final writing shouldn't throw warnings, but...
     V3Error::abortIfWarnings();
 
diff --git a/src/VlcOptions.h b/src/VlcOptions.h
index 3759a5445..17c2e1eed 100644
--- a/src/VlcOptions.h
+++ b/src/VlcOptions.h
@@ -74,7 +74,7 @@ public:
     bool rank() const { return m_rank; }
     bool unlink() const { return m_unlink; }
     string writeFile() const { return m_writeFile; }
-    
+
     // METHODS (from main)
     static string version();
 };
diff --git a/src/VlcTop.cpp b/src/VlcTop.cpp
index 8ddcf5208..6520b34d1 100644
--- a/src/VlcTop.cpp
+++ b/src/VlcTop.cpp
@@ -208,7 +208,7 @@ void VlcTop::annotateOutputFiles(const string& dirname) {
 	    v3error("Can't read "<<filename);
 	    return;
 	}
-	
+
 	ofstream os (outfilename.c_str());
 	if (!os) {
 	    v3fatal("Can't write "<<outfilename);
diff --git a/src/verilog.y b/src/verilog.y
index 8449cb2b2..47e50b56e 100644
--- a/src/verilog.y
+++ b/src/verilog.y
@@ -127,7 +127,7 @@ public:
 	    pkgp = PARSEP->rootp()->dollarUnitPkgAddp();
 	    SYMP->reinsert(pkgp, SYMP->symRootp());  // Don't push/pop scope as they're global
 	} else {
-	    pkgp = symp->nodep()->castPackage(); 
+	    pkgp = symp->nodep()->castPackage();
 	}
 	return pkgp;
     }
diff --git a/test_regress/t/t_array_packed_sysfunct.v b/test_regress/t/t_array_packed_sysfunct.v
index 65f101c52..03934588c 100644
--- a/test_regress/t/t_array_packed_sysfunct.v
+++ b/test_regress/t/t_array_packed_sysfunct.v
@@ -43,7 +43,7 @@ module t (/*AUTOARG*/
       `checkh($increment(array_unpk), 1);
       `checkh($size (array_unpk), 2);
    end
-   
+
    // event counter
    always @ (posedge clk) begin
       cnt <= cnt + 1;
@@ -165,5 +165,5 @@ module t (/*AUTOARG*/
 	 end
       end
    end
-   
+
 endmodule
diff --git a/test_regress/t/t_array_query.v b/test_regress/t/t_array_query.v
index f65bae653..d9a519966 100644
--- a/test_regress/t/t_array_query.v
+++ b/test_regress/t/t_array_query.v
@@ -17,7 +17,7 @@ module t (/*AUTOARG*/
    wire  a = clk;
    wire  b = 1'b0;
    reg   c;
-   
+
    array_test array_test_i (/*AUTOINST*/
 			    // Inputs
 			    .clk		(clk));
@@ -46,12 +46,12 @@ module array_test
    integer   l;
    integer   r;
    integer   s;
-   
+
    always @(posedge clk) begin
       l = $left (a);
       r = $right (a);
       s = $size (a);
-      
+
 `ifdef TEST_VERBOSE
       $write ("$left (a) = %d, $right (a) = %d, $size (a) = %d\n", l, r, s);
 `endif
diff --git a/test_regress/t/t_assert_cover.v b/test_regress/t/t_assert_cover.v
index 541423e5b..8d5e10391 100644
--- a/test_regress/t/t_assert_cover.v
+++ b/test_regress/t/t_assert_cover.v
@@ -41,7 +41,7 @@ module Test
    );
 
    // Simple cover
-   cover property (@(posedge clk) cyc==3); 
+   cover property (@(posedge clk) cyc==3);
 
    // With statement, in generate
    generate if (1) begin
@@ -51,16 +51,16 @@ module Test
 
    // Labeled cover
    cyc_eq_5:
-     cover property (@(posedge clk) cyc==5) $display("*COVER: Cyc==5"); 
+     cover property (@(posedge clk) cyc==5) $display("*COVER: Cyc==5");
 
    // Using default clock
    default clocking @(posedge clk); endclocking
-   cover property (cyc==6) $display("*COVER: Cyc==6"); 
+   cover property (cyc==6) $display("*COVER: Cyc==6");
 
    // Disable statement
    // Note () after disable are required
    cover property (@(posedge clk) disable iff (toggle) cyc==8)
-     $display("*COVER: Cyc==8"); 
+     $display("*COVER: Cyc==8");
    cover property (@(posedge clk) disable iff (!toggle) cyc==8)
      $stop;
 
@@ -86,7 +86,7 @@ module Test
 	disable iff (!toggle)
 	cyc==5;
    endproperty
-   cover property (C1) $display("*COVER: Cyc==5"); 
+   cover property (C1) $display("*COVER: Cyc==5");
 
    // Using covergroup
    // Note a covergroup is really inheritance of a special system "covergroup" class.
diff --git a/test_regress/t/t_assign_inline.v b/test_regress/t/t_assign_inline.v
index cc1f25c5a..5d29871a9 100644
--- a/test_regress/t/t_assign_inline.v
+++ b/test_regress/t/t_assign_inline.v
@@ -1,4 +1,4 @@
-// DESCRIPTION: Verilator: Verilog Test module 
+// DESCRIPTION: Verilator: Verilog Test module
 //
 // This file ONLY is placed into the Public Domain, for any use,
 // without warranty, 2015 by Mike Thyer.
@@ -8,17 +8,17 @@ module t (/*AUTOARG*/
    clk
    );
    input clk;
-   
+
    int cycle=0;
-      
+
    // verilator lint_off UNOPTFLAT
    reg  [7:0] a_r;
    wire [7:0] a_w;
    reg  [7:0] b_r;
    reg  [7:0] c_d_r, c_q_r;
-   
+
    assign a_w = a_r;
-    
+
    always @(*) begin
      a_r = 0;
      b_r = a_w;  // Substituting the a_w assignment to get b_r = 0 is wrong, as a_r is not "complete"
@@ -32,7 +32,7 @@ module t (/*AUTOARG*/
      if (cycle==0) begin
        c_q_r <= 8'b0;
      end
-     else begin 
+     else begin
        c_q_r <= c_d_r+1;
 `ifdef TEST_VERBOSE
        $display("[%0t] a_r=%0d, b_r=%0d", $time, a_r, b_r); // a_r and b_r should always be the same
diff --git a/test_regress/t/t_bench_mux4k.v b/test_regress/t/t_bench_mux4k.v
index 35ec670bc..5b4350ee6 100644
--- a/test_regress/t/t_bench_mux4k.v
+++ b/test_regress/t/t_bench_mux4k.v
@@ -27,7 +27,7 @@ module t (/*AUTOARG*/
    // Beginning of automatic wires (for undeclared instantiated-module outputs)
    wire [`DATA_WIDTH-1:0] datao;		// From mux4096 of mux4096.v
    // End of automatics
-   
+
    reg [`DATA_WIDTH*`MUX1_SIZE*`MUX2_SIZE-1:0] datai;
    reg [`ADDR_WIDTH-1:0] 		       addr;
 
@@ -130,7 +130,7 @@ module mux4096_1bit
       .C(F),
       .datai(data0),
       .datao(datao));
-   
+
 endmodule
 
 module mux64
@@ -147,12 +147,12 @@ module mux64
    wire [63:0] colSelC = { {16{C[3]}}, {16{C[2]}}, {16{C[1]}}, {16{C[0]}}};
 
    wire [MUX_SIZE-1:0] data_bus;
-   
+
    // Note each of these becomes a separate wire.
    //.colSelA(colSelA[MUX_SIZE-1:0]),
    //.colSelB(colSelB[MUX_SIZE-1:0]),
    //.colSelC(colSelC[MUX_SIZE-1:0]),
-   
+
    drv drv[MUX_SIZE-1:0]
      (.colSelA(colSelA[MUX_SIZE-1:0]),
       .colSelB(colSelB[MUX_SIZE-1:0]),
diff --git a/test_regress/t/t_bench_synmul.pl b/test_regress/t/t_bench_synmul.pl
index 418a9d009..29714537e 100755
--- a/test_regress/t/t_bench_synmul.pl
+++ b/test_regress/t/t_bench_synmul.pl
@@ -11,7 +11,7 @@ top_filename("t/t_math_synmul.v");
 
 $Self->{cycles} = $Self->{benchmark}||0;
 $Self->{cycles} = 100 if $Self->{cycles}<100;
-	      
+
 $Self->{sim_time} = $Self->{cycles}*100;
 
 compile (
diff --git a/test_regress/t/t_case_dupitems.v b/test_regress/t/t_case_dupitems.v
index c4c350166..b5d6a9bab 100644
--- a/test_regress/t/t_case_dupitems.v
+++ b/test_regress/t/t_case_dupitems.v
@@ -71,7 +71,7 @@ module Test (/*AUTOARG*/
    output reg [1:0] out;
    always @* begin
       // bug99: Internal Error: ../V3Ast.cpp:495: New node already linked?
-      case (in[1:0]) 
+      case (in[1:0])
 	2'd0, 2'd1, 2'd2, 2'd3: begin
 	   out = in;
 	end
diff --git a/test_regress/t/t_case_huge_sub3.v b/test_regress/t/t_case_huge_sub3.v
index 0c6374982..746344f3d 100644
--- a/test_regress/t/t_case_huge_sub3.v
+++ b/test_regress/t/t_case_huge_sub3.v
@@ -5,7 +5,7 @@
 
 module t_case_huge_sub3 (/*AUTOARG*/
    // Outputs
-   outr, 
+   outr,
    // Inputs
    clk, index
    );
diff --git a/test_regress/t/t_case_reducer.v b/test_regress/t/t_case_reducer.v
index 56911f9d3..b96570a9d 100644
--- a/test_regress/t/t_case_reducer.v
+++ b/test_regress/t/t_case_reducer.v
@@ -73,7 +73,7 @@ module Test
 	     // Outputs
    output wire [6:0] out
    );
-  
+
    wire [6:0] 	     clz_a;
    wire [6:0] 	     clz_b;
 
@@ -89,10 +89,10 @@ module Test
      .data_i      (operand_b),
      .out      (clz_b));
 
-   assign out     = clz_a - clz_b;  
+   assign out     = clz_a - clz_b;
 `ifdef TEST_VERBOSE
-   always @(posedge clk) 
-     $display("Out(%x) =  clz_a(%x) - clz_b(%x)", out, clz_a, clz_b);  
+   always @(posedge clk)
+     $display("Out(%x) =  clz_a(%x) - clz_b(%x)", out, clz_a, clz_b);
 `endif
 
 endmodule
@@ -231,7 +231,7 @@ module clz(
       8'b0000_0000   : clz_byte0 = 3'b111;
       default        : clz_byte0 = 3'bxxx;
     endcase
-    
+
   always @*
     case (data_i)
       `def_1xxx_xxxx : clz_byte1 = 3'b000;
diff --git a/test_regress/t/t_cellarray.v b/test_regress/t/t_cellarray.v
index 0d2a62dfb..3be5db87b 100644
--- a/test_regress/t/t_cellarray.v
+++ b/test_regress/t/t_cellarray.v
@@ -5,7 +5,7 @@
 //
 
 // change these two parameters to see the speed differences
-`define DATA_WIDTH 8 
+`define DATA_WIDTH 8
 `define REP_COUNT4 `DATA_WIDTH/4
 `define REP_COUNT2 `DATA_WIDTH/2
 
@@ -17,7 +17,7 @@ module t (/*AUTOARG*/
    input clk;
    reg [3:0] count4 = 0;
    reg [1:0] count2 = 0;
- 
+
    reg [`DATA_WIDTH-1:0] a = {`REP_COUNT4{4'b0000}};
    reg [`DATA_WIDTH-1:0] b = {`REP_COUNT4{4'b1111}};
    reg [`DATA_WIDTH-1:0] c = {`REP_COUNT4{4'b1111}};
diff --git a/test_regress/t/t_clk_2in.pl b/test_regress/t/t_clk_2in.pl
index b8ca2bb72..c06cdc013 100755
--- a/test_regress/t/t_clk_2in.pl
+++ b/test_regress/t/t_clk_2in.pl
@@ -11,7 +11,7 @@ compile (
     make_top_shell => 0,
     make_main => 0,
     verilator_flags2 => ["--exe","$Self->{t_dir}/$Self->{name}.cpp"],
-    vcs_flags2 => ['-assert'],	
+    vcs_flags2 => ['-assert'],
     );
 
 execute (
diff --git a/test_regress/t/t_clk_concat6.v b/test_regress/t/t_clk_concat6.v
index 106bb3de6..49acb3d6f 100644
--- a/test_regress/t/t_clk_concat6.v
+++ b/test_regress/t/t_clk_concat6.v
@@ -11,7 +11,7 @@ module some_module (
    logic [ 1 : 0 ] 		some_state;
    logic [1:0] 			some_other_state;
    logic 			the_clk;
-   
+
    assign the_clk = i_clks[3];
 
    always @(posedge the_clk) begin
diff --git a/test_regress/t/t_clocker.v b/test_regress/t/t_clocker.v
index 4a8b3f408..1385119b8 100644
--- a/test_regress/t/t_clocker.v
+++ b/test_regress/t/t_clocker.v
@@ -38,7 +38,7 @@ module t (/*AUTOARG*/
    assign clk_final = clk_3[0];
 
    // the following two assignment triggers the CLKDATA warning
-   // because on LHS there are a mix of signals both CLOCK and 
+   // because on LHS there are a mix of signals both CLOCK and
    // DATA
    /* verilator lint_off CLKDATA */
    assign res8  = {clk_3, 1'b0, clk_4};
@@ -46,7 +46,7 @@ module t (/*AUTOARG*/
    /* verilator lint_on CLKDATA */
 
 
-   initial 
+   initial
        count = 0;
 
 
diff --git a/test_regress/t/t_concat_opt.v b/test_regress/t/t_concat_opt.v
index fe723f2dd..900a36f68 100644
--- a/test_regress/t/t_concat_opt.v
+++ b/test_regress/t/t_concat_opt.v
@@ -3,7 +3,7 @@
 // This file ONLY is placed into the Public Domain, for any use,
 // without warranty, 2004 by Jie Xu.
 //
-// The test was added together with the concat optimization. 
+// The test was added together with the concat optimization.
 
 module t (/*AUTOARG*/
    // Inputs
diff --git a/test_regress/t/t_const_overflow_bad.v b/test_regress/t/t_const_overflow_bad.v
index 26698da66..872a5717b 100644
--- a/test_regress/t/t_const_overflow_bad.v
+++ b/test_regress/t/t_const_overflow_bad.v
@@ -10,7 +10,7 @@ module t (/*AUTOARG*/);
    parameter [200:0] SMALLH = 8'habc;  // One to many digits
    parameter [200:0] SMALLO = 6'o1234;  // One to many digits
    parameter [200:0] SMALLB = 3'b1111;  // One to many digits
-   
+
    // We'll allow this though; no reason to be cruel
    parameter [200:0] OKH = 8'h000000001;
 
diff --git a/test_regress/t/t_cover_sva_notflat.v b/test_regress/t/t_cover_sva_notflat.v
index a626ea7fc..59f920723 100644
--- a/test_regress/t/t_cover_sva_notflat.v
+++ b/test_regress/t/t_cover_sva_notflat.v
@@ -54,6 +54,6 @@ module Test
    // verilator no_inline_module
 
    // Labeled cover
-   cyc_eq_5: cover property (@(posedge clk) cyc==5) $display("*COVER: Cyc==5"); 
+   cyc_eq_5: cover property (@(posedge clk) cyc==5) $display("*COVER: Cyc==5");
 
 endmodule
diff --git a/test_regress/t/t_display.pl b/test_regress/t/t_display.pl
index 3ee1a9dd1..d51c86440 100755
--- a/test_regress/t/t_display.pl
+++ b/test_regress/t/t_display.pl
@@ -31,8 +31,8 @@ q{[0] In top.t: Hi
 [0] %X=00c %0X=c  %X=00abbbbcccc %0X=abbbbcccc  %X=00abc1234567812345678 %0X=abc1234567812345678
 [0] %C=m %0C=m
 [0] %c=m %0c=m
-[0] %v=St0 St0 St0 St0 St0 St1 St1 St0 St0  %0v=St0 St0 St0 St0 St0 St1 St1 St0 St0   %v=St0 St0 St0 St0 St0 St1 St0 St1 St0 St1 St0 St1 St1 St1 St0 St1 St1 St1 St0 St1 St1 St1 St0 St1 St1 St1 St1 St0 St0 St1 St1 St0 St0 St1 St1 St0 St0 St1 St1 St0 St0  %0v=St0 St0 St0 St0 St0 St1 St0 St1 St0 St1 St0 St1 St1 St1 St0 St1 St1 St1 St0 St1 St1 St1 St0 St1 St1 St1 St1 St0 St0 St1 St1 St0 St0 St1 St1 St0 St0 St1 St1 St0 St0   %v=St0 St0 St0 St0 St0 St1 St0 St1 St0 St1 St0 St1 St1 St1 St1 St0 St0 St0 St0 St0 St1 St0 St0 St1 St0 St0 St0 St1 St1 St0 St1 St0 St0 St0 St1 St0 St1 St0 St1 St1 St0 St0 St1 St1 St1 St1 St0 St0 St0 St0 St0 St0 St1 St0 St0 St1 St0 St0 St0 St1 St1 St0 St1 St0 St0 St0 St1 St0 St1 St0 St1 St1 St0 St0 St1 St1 St1 St1 St0 St0 St0  %0v=St0 St0 St0 St0 St0 St1 St0 St1 St0 St1 St0 St1 St1 St1 St1 St0 St0 St0 St0 St0 St1 St0 St0 St1 St0 St0 St0 St1 St1 St0 St1 St0 St0 St0 St1 St0 St1 St0 St1 St1 St0 St0 St1 St1 St1 St1 St0 St0 St0 St0 St0 St0 St1 St0 St0 St1 St0 St0 St0 St1 St1 St0 St1 St0 St0 St0 St1 St0 St1 St0 St1 St1 St0 St0 St1 St1 St1 St1 St0 St0 St0 
-[0] %V=St0 St0 St0 St0 St0 St1 St1 St0 St0  %0V=St0 St0 St0 St0 St0 St1 St1 St0 St0   %V=St0 St0 St0 St0 St0 St1 St0 St1 St0 St1 St0 St1 St1 St1 St0 St1 St1 St1 St0 St1 St1 St1 St0 St1 St1 St1 St1 St0 St0 St1 St1 St0 St0 St1 St1 St0 St0 St1 St1 St0 St0  %0V=St0 St0 St0 St0 St0 St1 St0 St1 St0 St1 St0 St1 St1 St1 St0 St1 St1 St1 St0 St1 St1 St1 St0 St1 St1 St1 St1 St0 St0 St1 St1 St0 St0 St1 St1 St0 St0 St1 St1 St0 St0   %V=St0 St0 St0 St0 St0 St1 St0 St1 St0 St1 St0 St1 St1 St1 St1 St0 St0 St0 St0 St0 St1 St0 St0 St1 St0 St0 St0 St1 St1 St0 St1 St0 St0 St0 St1 St0 St1 St0 St1 St1 St0 St0 St1 St1 St1 St1 St0 St0 St0 St0 St0 St0 St1 St0 St0 St1 St0 St0 St0 St1 St1 St0 St1 St0 St0 St0 St1 St0 St1 St0 St1 St1 St0 St0 St1 St1 St1 St1 St0 St0 St0  %0V=St0 St0 St0 St0 St0 St1 St0 St1 St0 St1 St0 St1 St1 St1 St1 St0 St0 St0 St0 St0 St1 St0 St0 St1 St0 St0 St0 St1 St1 St0 St1 St0 St0 St0 St1 St0 St1 St0 St1 St1 St0 St0 St1 St1 St1 St1 St0 St0 St0 St0 St0 St0 St1 St0 St0 St1 St0 St0 St0 St1 St1 St0 St1 St0 St0 St0 St1 St0 St1 St0 St1 St1 St0 St0 St1 St1 St1 St1 St0 St0 St0 
+[0] %v=St0 St0 St0 St0 St0 St1 St1 St0 St0  %0v=St0 St0 St0 St0 St0 St1 St1 St0 St0   %v=St0 St0 St0 St0 St0 St1 St0 St1 St0 St1 St0 St1 St1 St1 St0 St1 St1 St1 St0 St1 St1 St1 St0 St1 St1 St1 St1 St0 St0 St1 St1 St0 St0 St1 St1 St0 St0 St1 St1 St0 St0  %0v=St0 St0 St0 St0 St0 St1 St0 St1 St0 St1 St0 St1 St1 St1 St0 St1 St1 St1 St0 St1 St1 St1 St0 St1 St1 St1 St1 St0 St0 St1 St1 St0 St0 St1 St1 St0 St0 St1 St1 St0 St0   %v=St0 St0 St0 St0 St0 St1 St0 St1 St0 St1 St0 St1 St1 St1 St1 St0 St0 St0 St0 St0 St1 St0 St0 St1 St0 St0 St0 St1 St1 St0 St1 St0 St0 St0 St1 St0 St1 St0 St1 St1 St0 St0 St1 St1 St1 St1 St0 St0 St0 St0 St0 St0 St1 St0 St0 St1 St0 St0 St0 St1 St1 St0 St1 St0 St0 St0 St1 St0 St1 St0 St1 St1 St0 St0 St1 St1 St1 St1 St0 St0 St0  %0v=St0 St0 St0 St0 St0 St1 St0 St1 St0 St1 St0 St1 St1 St1 St1 St0 St0 St0 St0 St0 St1 St0 St0 St1 St0 St0 St0 St1 St1 St0 St1 St0 St0 St0 St1 St0 St1 St0 St1 St1 St0 St0 St1 St1 St1 St1 St0 St0 St0 St0 St0 St0 St1 St0 St0 St1 St0 St0 St0 St1 St1 St0 St1 St0 St0 St0 St1 St0 St1 St0 St1 St1 St0 St0 St1 St1 St1 St1 St0 St0 St0  <
+[0] %V=St0 St0 St0 St0 St0 St1 St1 St0 St0  %0V=St0 St0 St0 St0 St0 St1 St1 St0 St0   %V=St0 St0 St0 St0 St0 St1 St0 St1 St0 St1 St0 St1 St1 St1 St0 St1 St1 St1 St0 St1 St1 St1 St0 St1 St1 St1 St1 St0 St0 St1 St1 St0 St0 St1 St1 St0 St0 St1 St1 St0 St0  %0V=St0 St0 St0 St0 St0 St1 St0 St1 St0 St1 St0 St1 St1 St1 St0 St1 St1 St1 St0 St1 St1 St1 St0 St1 St1 St1 St1 St0 St0 St1 St1 St0 St0 St1 St1 St0 St0 St1 St1 St0 St0   %V=St0 St0 St0 St0 St0 St1 St0 St1 St0 St1 St0 St1 St1 St1 St1 St0 St0 St0 St0 St0 St1 St0 St0 St1 St0 St0 St0 St1 St1 St0 St1 St0 St0 St0 St1 St0 St1 St0 St1 St1 St0 St0 St1 St1 St1 St1 St0 St0 St0 St0 St0 St0 St1 St0 St0 St1 St0 St0 St0 St1 St1 St0 St1 St0 St0 St0 St1 St0 St1 St0 St1 St1 St0 St0 St1 St1 St1 St1 St0 St0 St0  %0V=St0 St0 St0 St0 St0 St1 St0 St1 St0 St1 St0 St1 St1 St1 St1 St0 St0 St0 St0 St0 St1 St0 St0 St1 St0 St0 St0 St1 St1 St0 St1 St0 St0 St0 St1 St0 St1 St0 St1 St1 St0 St0 St1 St1 St1 St1 St0 St0 St0 St0 St0 St0 St1 St0 St0 St1 St0 St0 St0 St1 St1 St0 St1 St0 St0 St0 St1 St0 St1 St0 St1 St1 St0 St0 St1 St1 St1 St1 St0 St0 St0  <
 [0] %p='hc %0p='hc  %p='habbbbcccc %0p='habbbbcccc  %p='habc1234567812345678 %0p='habc1234567812345678
 [0] %P='hc %0P='hc  %P='habbbbcccc %0P='habbbbcccc  %P='habc1234567812345678 %0P='habc1234567812345678
 [0] %P="sv-str"
diff --git a/test_regress/t/t_display.v b/test_regress/t/t_display.v
index 0c16b3191..450d6d130 100644
--- a/test_regress/t/t_display.v
+++ b/test_regress/t/t_display.v
@@ -52,9 +52,9 @@ module t;
 	       "a"+nine, "a"+nine);
       // verilator lint_on WIDTH
 
-      $display("[%0t] %%v=%v %%0v=%0v  %%v=%v %%0v=%0v  %%v=%v %%0v=%0v", $time,
+      $display("[%0t] %%v=%v %%0v=%0v  %%v=%v %%0v=%0v  %%v=%v %%0v=%0v <", $time,
 	       nine, nine, quad, quad, wide, wide);
-      $display("[%0t] %%V=%V %%0V=%0V  %%V=%V %%0V=%0V  %%V=%V %%0V=%0V", $time,
+      $display("[%0t] %%V=%V %%0V=%0V  %%V=%V %%0V=%0V  %%V=%V %%0V=%0V <", $time,
 	       nine, nine, quad, quad, wide, wide);
       $display("[%0t] %%p=%p %%0p=%0p  %%p=%p %%0p=%0p  %%p=%p %%0p=%0p", $time,
 	       nine, nine, quad, quad, wide, wide);
diff --git a/test_regress/t/t_display_noopt.pl b/test_regress/t/t_display_noopt.pl
index 664b0166e..d53170428 100755
--- a/test_regress/t/t_display_noopt.pl
+++ b/test_regress/t/t_display_noopt.pl
@@ -34,8 +34,8 @@ q{[0] In top.t: Hi
 [0] %X=00c %0X=c  %X=00abbbbcccc %0X=abbbbcccc  %X=00abc1234567812345678 %0X=abc1234567812345678
 [0] %C=m %0C=m
 [0] %c=m %0c=m
-[0] %v=St0 St0 St0 St0 St0 St1 St1 St0 St0  %0v=St0 St0 St0 St0 St0 St1 St1 St0 St0   %v=St0 St0 St0 St0 St0 St1 St0 St1 St0 St1 St0 St1 St1 St1 St0 St1 St1 St1 St0 St1 St1 St1 St0 St1 St1 St1 St1 St0 St0 St1 St1 St0 St0 St1 St1 St0 St0 St1 St1 St0 St0  %0v=St0 St0 St0 St0 St0 St1 St0 St1 St0 St1 St0 St1 St1 St1 St0 St1 St1 St1 St0 St1 St1 St1 St0 St1 St1 St1 St1 St0 St0 St1 St1 St0 St0 St1 St1 St0 St0 St1 St1 St0 St0   %v=St0 St0 St0 St0 St0 St1 St0 St1 St0 St1 St0 St1 St1 St1 St1 St0 St0 St0 St0 St0 St1 St0 St0 St1 St0 St0 St0 St1 St1 St0 St1 St0 St0 St0 St1 St0 St1 St0 St1 St1 St0 St0 St1 St1 St1 St1 St0 St0 St0 St0 St0 St0 St1 St0 St0 St1 St0 St0 St0 St1 St1 St0 St1 St0 St0 St0 St1 St0 St1 St0 St1 St1 St0 St0 St1 St1 St1 St1 St0 St0 St0  %0v=St0 St0 St0 St0 St0 St1 St0 St1 St0 St1 St0 St1 St1 St1 St1 St0 St0 St0 St0 St0 St1 St0 St0 St1 St0 St0 St0 St1 St1 St0 St1 St0 St0 St0 St1 St0 St1 St0 St1 St1 St0 St0 St1 St1 St1 St1 St0 St0 St0 St0 St0 St0 St1 St0 St0 St1 St0 St0 St0 St1 St1 St0 St1 St0 St0 St0 St1 St0 St1 St0 St1 St1 St0 St0 St1 St1 St1 St1 St0 St0 St0 
-[0] %V=St0 St0 St0 St0 St0 St1 St1 St0 St0  %0V=St0 St0 St0 St0 St0 St1 St1 St0 St0   %V=St0 St0 St0 St0 St0 St1 St0 St1 St0 St1 St0 St1 St1 St1 St0 St1 St1 St1 St0 St1 St1 St1 St0 St1 St1 St1 St1 St0 St0 St1 St1 St0 St0 St1 St1 St0 St0 St1 St1 St0 St0  %0V=St0 St0 St0 St0 St0 St1 St0 St1 St0 St1 St0 St1 St1 St1 St0 St1 St1 St1 St0 St1 St1 St1 St0 St1 St1 St1 St1 St0 St0 St1 St1 St0 St0 St1 St1 St0 St0 St1 St1 St0 St0   %V=St0 St0 St0 St0 St0 St1 St0 St1 St0 St1 St0 St1 St1 St1 St1 St0 St0 St0 St0 St0 St1 St0 St0 St1 St0 St0 St0 St1 St1 St0 St1 St0 St0 St0 St1 St0 St1 St0 St1 St1 St0 St0 St1 St1 St1 St1 St0 St0 St0 St0 St0 St0 St1 St0 St0 St1 St0 St0 St0 St1 St1 St0 St1 St0 St0 St0 St1 St0 St1 St0 St1 St1 St0 St0 St1 St1 St1 St1 St0 St0 St0  %0V=St0 St0 St0 St0 St0 St1 St0 St1 St0 St1 St0 St1 St1 St1 St1 St0 St0 St0 St0 St0 St1 St0 St0 St1 St0 St0 St0 St1 St1 St0 St1 St0 St0 St0 St1 St0 St1 St0 St1 St1 St0 St0 St1 St1 St1 St1 St0 St0 St0 St0 St0 St0 St1 St0 St0 St1 St0 St0 St0 St1 St1 St0 St1 St0 St0 St0 St1 St0 St1 St0 St1 St1 St0 St0 St1 St1 St1 St1 St0 St0 St0 
+[0] %v=St0 St0 St0 St0 St0 St1 St1 St0 St0  %0v=St0 St0 St0 St0 St0 St1 St1 St0 St0   %v=St0 St0 St0 St0 St0 St1 St0 St1 St0 St1 St0 St1 St1 St1 St0 St1 St1 St1 St0 St1 St1 St1 St0 St1 St1 St1 St1 St0 St0 St1 St1 St0 St0 St1 St1 St0 St0 St1 St1 St0 St0  %0v=St0 St0 St0 St0 St0 St1 St0 St1 St0 St1 St0 St1 St1 St1 St0 St1 St1 St1 St0 St1 St1 St1 St0 St1 St1 St1 St1 St0 St0 St1 St1 St0 St0 St1 St1 St0 St0 St1 St1 St0 St0   %v=St0 St0 St0 St0 St0 St1 St0 St1 St0 St1 St0 St1 St1 St1 St1 St0 St0 St0 St0 St0 St1 St0 St0 St1 St0 St0 St0 St1 St1 St0 St1 St0 St0 St0 St1 St0 St1 St0 St1 St1 St0 St0 St1 St1 St1 St1 St0 St0 St0 St0 St0 St0 St1 St0 St0 St1 St0 St0 St0 St1 St1 St0 St1 St0 St0 St0 St1 St0 St1 St0 St1 St1 St0 St0 St1 St1 St1 St1 St0 St0 St0  %0v=St0 St0 St0 St0 St0 St1 St0 St1 St0 St1 St0 St1 St1 St1 St1 St0 St0 St0 St0 St0 St1 St0 St0 St1 St0 St0 St0 St1 St1 St0 St1 St0 St0 St0 St1 St0 St1 St0 St1 St1 St0 St0 St1 St1 St1 St1 St0 St0 St0 St0 St0 St0 St1 St0 St0 St1 St0 St0 St0 St1 St1 St0 St1 St0 St0 St0 St1 St0 St1 St0 St1 St1 St0 St0 St1 St1 St1 St1 St0 St0 St0  <
+[0] %V=St0 St0 St0 St0 St0 St1 St1 St0 St0  %0V=St0 St0 St0 St0 St0 St1 St1 St0 St0   %V=St0 St0 St0 St0 St0 St1 St0 St1 St0 St1 St0 St1 St1 St1 St0 St1 St1 St1 St0 St1 St1 St1 St0 St1 St1 St1 St1 St0 St0 St1 St1 St0 St0 St1 St1 St0 St0 St1 St1 St0 St0  %0V=St0 St0 St0 St0 St0 St1 St0 St1 St0 St1 St0 St1 St1 St1 St0 St1 St1 St1 St0 St1 St1 St1 St0 St1 St1 St1 St1 St0 St0 St1 St1 St0 St0 St1 St1 St0 St0 St1 St1 St0 St0   %V=St0 St0 St0 St0 St0 St1 St0 St1 St0 St1 St0 St1 St1 St1 St1 St0 St0 St0 St0 St0 St1 St0 St0 St1 St0 St0 St0 St1 St1 St0 St1 St0 St0 St0 St1 St0 St1 St0 St1 St1 St0 St0 St1 St1 St1 St1 St0 St0 St0 St0 St0 St0 St1 St0 St0 St1 St0 St0 St0 St1 St1 St0 St1 St0 St0 St0 St1 St0 St1 St0 St1 St1 St0 St0 St1 St1 St1 St1 St0 St0 St0  %0V=St0 St0 St0 St0 St0 St1 St0 St1 St0 St1 St0 St1 St1 St1 St1 St0 St0 St0 St0 St0 St1 St0 St0 St1 St0 St0 St0 St1 St1 St0 St1 St0 St0 St0 St1 St0 St1 St0 St1 St1 St0 St0 St1 St1 St1 St1 St0 St0 St0 St0 St0 St0 St1 St0 St0 St1 St0 St0 St0 St1 St1 St0 St1 St0 St0 St0 St1 St0 St1 St0 St1 St1 St0 St0 St1 St1 St1 St1 St0 St0 St0  <
 [0] %p='hc %0p='hc  %p='habbbbcccc %0p='habbbbcccc  %p='habc1234567812345678 %0p='habc1234567812345678
 [0] %P='hc %0P='hc  %P='habbbbcccc %0P='habbbbcccc  %P='habc1234567812345678 %0P='habc1234567812345678
 [0] %P="sv-str"
diff --git a/test_regress/t/t_dist_manifest.pl b/test_regress/t/t_dist_manifest.pl
index a38dfaf15..619c7da6a 100755
--- a/test_regress/t/t_dist_manifest.pl
+++ b/test_regress/t/t_dist_manifest.pl
@@ -11,16 +11,7 @@ my $root = "..";
 my $Debug;
 
 ### Must trim output before and after our file list
-`cd $root && make dist-file-list`;
-my $manifest_files = `cd $root && make dist-file-list`;
-$manifest_files =~ s!.*begin-dist-file-list:!!sg;
-$manifest_files =~ s!end-dist-file-list:.*$!!sg;
-print "MF $manifest_files\n";
-my %files;
-foreach my $file (split /\s+/,$manifest_files) {
-    next if $file eq '';
-    $files{$file} |= 1;
-}
+my %files = %{get_manifest_files($root)};
 
 my $all_files = `cd $root && find . -type f -print`;
 foreach my $file (split /\s+/,$all_files) {
@@ -70,3 +61,18 @@ if (keys %warns) {
 
 ok(1);
 1;
+
+sub get_manifest_files {
+    my $root = shift;
+    `cd $root && make dist-file-list`;
+    my $manifest_files = `cd $root && make dist-file-list`;
+    $manifest_files =~ s!.*begin-dist-file-list:!!sg;
+    $manifest_files =~ s!end-dist-file-list:.*$!!sg;
+    print "MF $manifest_files\n";
+    my %files;
+    foreach my $file (split /\s+/,$manifest_files) {
+	next if $file eq '';
+	$files{$file} |= 1;
+    }
+    return \%files;
+}
diff --git a/test_regress/t/t_dist_whitespace.pl b/test_regress/t/t_dist_whitespace.pl
new file mode 100755
index 000000000..67ff3534b
--- /dev/null
+++ b/test_regress/t/t_dist_whitespace.pl
@@ -0,0 +1,51 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+
+my $root = "..";
+my $Debug;
+
+### Must trim output before and after our file list
+my %files = %{get_manifest_files($root)};
+
+foreach my $file (sort keys %files) {
+    my $contents = file_contents("$root/$file");
+    if ($file =~ /\.out$/) {
+	# Ignore golden files
+    } elsif ($contents =~ /[\001\002\003\004\005\006]/) {
+	# Ignore binrary files
+    } elsif ($contents =~ /[ \t]\n/) {
+	$warns{$file} = "File contains trailing whitespace: $file";
+    }
+}
+
+if (keys %warns) {
+    # First warning lists everything as that's shown in the driver summary
+    $Self->error("Files have whitespace errors: ",join(' ',sort keys %warns));
+    foreach my $file (sort keys %warns) {
+	$Self->error($warns{$file});
+    }
+}
+
+ok(1);
+1;
+
+sub get_manifest_files {
+    my $root = shift;
+    `cd $root && make dist-file-list`;
+    my $manifest_files = `cd $root && make dist-file-list`;
+    $manifest_files =~ s!.*begin-dist-file-list:!!sg;
+    $manifest_files =~ s!end-dist-file-list:.*$!!sg;
+    print "MF $manifest_files\n";
+    my %files;
+    foreach my $file (split /\s+/,$manifest_files) {
+	next if $file eq '';
+	$files{$file} |= 1;
+    }
+    return \%files;
+}
diff --git a/test_regress/t/t_dpi_context.v b/test_regress/t/t_dpi_context.v
index d428a94d7..d92fff4c6 100644
--- a/test_regress/t/t_dpi_context.v
+++ b/test_regress/t/t_dpi_context.v
@@ -45,7 +45,7 @@ module sub (input integer inst);
       result = dpic_save(23+inst);
       if (result==0) $stop;
    endtask
-   
+
    task test2;
       if (dpic_restore() != 23+inst) $stop;
    endtask
diff --git a/test_regress/t/t_dpi_display.pl b/test_regress/t/t_dpi_display.pl
index ac27ec314..f2c032f05 100755
--- a/test_regress/t/t_dpi_display.pl
+++ b/test_regress/t/t_dpi_display.pl
@@ -14,16 +14,16 @@ compile (
 execute (
 	 check_finished=>1,
 	 expect=>quotemeta(
-q{dpii_display_call: 
-dpii_display_call: c
-dpii_display_call: co
-dpii_display_call: cons
-dpii_display_call: constant
-dpii_display_call: constant_value
-one10=0000000a 
-dpii_display_call: one10=0000000a 
-Mod=top.t 16=         10 10=0000000a 
-dpii_display_call: Mod=top.t 16=         10 10=0000000a 
+q{dpii_display_call: ''
+dpii_display_call: 'c'
+dpii_display_call: 'co'
+dpii_display_call: 'cons'
+dpii_display_call: 'constant'
+dpii_display_call: 'constant_value'
+one10=0000000a
+dpii_display_call: 'one10=0000000a'
+Mod=top.t 16=         10 10=0000000a
+dpii_display_call: 'Mod=top.t 16=         10 10=0000000a'
 *-* All Finished *-*
 }),
      );
diff --git a/test_regress/t/t_dpi_display.v b/test_regress/t/t_dpi_display.v
index a307130e1..3fc8f1a08 100644
--- a/test_regress/t/t_dpi_display.v
+++ b/test_regress/t/t_dpi_display.v
@@ -26,10 +26,10 @@ module t ();
       $dpii_display("constant_value");
 
       a = $c("10");  // Don't optimize away "a"
-      $display     ("one10=%x ",a);  // Check single arg
-      $dpii_display("one10=%x ",a);
-      $display     ("Mod=%m 16=%d 10=%x ",a,a); // Check multiarg
-      $dpii_display("Mod=%m 16=%d 10=%x ",a,a);
+      $display     ("one10=%x",a);  // Check single arg
+      $dpii_display("one10=%x",a);
+      $display     ("Mod=%m 16=%d 10=%x",a,a); // Check multiarg
+      $dpii_display("Mod=%m 16=%d 10=%x",a,a);
 
       $write("*-* All Finished *-*\n");
       $finish;
diff --git a/test_regress/t/t_dpi_display_c.cpp b/test_regress/t/t_dpi_display_c.cpp
index 39a38d53d..88e779786 100644
--- a/test_regress/t/t_dpi_display_c.cpp
+++ b/test_regress/t/t_dpi_display_c.cpp
@@ -38,5 +38,5 @@ extern "C" {
 //======================================================================
 
 void dpii_display_call(const char* c) {
-    VL_PRINTF("dpii_display_call: %s\n", c);
+    VL_PRINTF("dpii_display_call: '%s'\n", c);
 }
diff --git a/test_regress/t/t_dpi_imp_gen.v b/test_regress/t/t_dpi_imp_gen.v
index 1a6527c1c..2e4367888 100644
--- a/test_regress/t/t_dpi_imp_gen.v
+++ b/test_regress/t/t_dpi_imp_gen.v
@@ -29,5 +29,5 @@ module t (/*AUTOARG*/
       $write("*-* All Finished *-*\n");
       $finish;
    end
-   
+
 endmodule
diff --git a/test_regress/t/t_dpi_shortcircuit2.v b/test_regress/t/t_dpi_shortcircuit2.v
index 602bdf9c2..1ec645f87 100644
--- a/test_regress/t/t_dpi_shortcircuit2.v
+++ b/test_regress/t/t_dpi_shortcircuit2.v
@@ -51,7 +51,7 @@ module t (/*AUTOARG*/);
       for (i=0; i<64; i++) begin
 	 if (i[0])
 	   j = 0;
-	 else 
+	 else
 	   j = {31'b0, dpii_inc1(0)};
 	 k = k + j;
       end
diff --git a/test_regress/t/t_dpi_vams.v b/test_regress/t/t_dpi_vams.v
index 4621d82ec..09d458043 100644
--- a/test_regress/t/t_dpi_vams.v
+++ b/test_regress/t/t_dpi_vams.v
@@ -15,12 +15,12 @@ module t (/*AUTOARG*/
 
    input in;
    wreal in;
-   output out; 
-   wreal out; 
+   output out;
+   wreal out;
 
    import "DPI-C" context function void dpii_call(input real in, output real out);
 
-   initial begin 
+   initial begin
       dpii_call(in,out);
       $finish;
    end
diff --git a/test_regress/t/t_embed1.pl b/test_regress/t/t_embed1.pl
index 9abaa2684..c6d99cb07 100755
--- a/test_regress/t/t_embed1.pl
+++ b/test_regress/t/t_embed1.pl
@@ -20,7 +20,7 @@ mkdir $child_dir;
 	 top_filename => "$Self->{name}_child.v",
 	 verilator_flags => ["-cc", "-Mdir", "${child_dir}", "--debug-check"],
 	);
-    
+
     $Self->_run(logfile=>"${child_dir}/vlt_compile.log",
 		cmd=>\@cmdargs);
 
diff --git a/test_regress/t/t_embed1_c.cpp b/test_regress/t/t_embed1_c.cpp
index 163ce6d3f..673130a22 100644
--- a/test_regress/t/t_embed1_c.cpp
+++ b/test_regress/t/t_embed1_c.cpp
@@ -64,7 +64,7 @@ Vt_embed1_child* __get_modelp() {
 	    vl_fatal(__FILE__,__LINE__,__FILE__,"svPutUserData failed");
 	}
     }
-    return (Vt_embed1_child*)(__modelp); 
+    return (Vt_embed1_child*)(__modelp);
 }
 
 void t_embed_child_initial() {
diff --git a/test_regress/t/t_embed1_child.v b/test_regress/t/t_embed1_child.v
index b7b493b21..84f118ae3 100644
--- a/test_regress/t/t_embed1_child.v
+++ b/test_regress/t/t_embed1_child.v
@@ -20,7 +20,7 @@ module t_embed1_child (/*AUTOARG*/
    output 	  did_init_out;
 
    input 	  is_ref;
-   
+
    reg did_init; initial did_init = 0;
    initial begin
       did_init = 1;
diff --git a/test_regress/t/t_embed1_wrap.v b/test_regress/t/t_embed1_wrap.v
index 9be795fa9..9afca7bf9 100644
--- a/test_regress/t/t_embed1_wrap.v
+++ b/test_regress/t/t_embed1_wrap.v
@@ -22,8 +22,8 @@ module t_embed1_wrap (/*AUTOARG*/
    input [123:0]	wide_in;
    input		is_ref;
    // End of automatics
-   
-`ifdef verilator   
+
+`ifdef verilator
    // Import $t_embed_child__initial etc as a DPI function
 `endif
 
diff --git a/test_regress/t/t_enum_large_methods.v b/test_regress/t/t_enum_large_methods.v
index 95056c54e..0e338cafd 100644
--- a/test_regress/t/t_enum_large_methods.v
+++ b/test_regress/t/t_enum_large_methods.v
@@ -31,13 +31,13 @@ module t (/*AUTOARG*/
       end
       else if (cyc==1) begin
 	 `checks(e.name, "E01");
-	 `checkh(e.next, ELARGE); 
+	 `checkh(e.next, ELARGE);
 	 e <= ELARGE;
       end
       else if (cyc==3) begin
 	 `checks(e.name, "ELARGE");
-	 `checkh(e.next, E01); 
-	 `checkh(e.prev, E01); 
+	 `checkh(e.next, E01);
+	 `checkh(e.prev, E01);
 	 e <= E01;
       end
       else if (cyc==20) begin
diff --git a/test_regress/t/t_enum_type_methods.v b/test_regress/t/t_enum_type_methods.v
index 431244ac7..27139526c 100644
--- a/test_regress/t/t_enum_type_methods.v
+++ b/test_regress/t/t_enum_type_methods.v
@@ -31,13 +31,13 @@ module t (/*AUTOARG*/
       `checkh(e.first, E01);
       `checkh(e.last, E04);
       `checkh(e.last(), E04);
-      `checkh(e.next, E04); 
-      `checkh(e.next(), E04); 
-      `checkh(e.next(1), E04); 
-      //Unsup: `checkh(e.next(2), E01); 
-      `checkh(e.prev, E01); 
-      `checkh(e.prev(1), E01); 
-      //Unsup: `checkh(e.prev(2), E04); 
+      `checkh(e.next, E04);
+      `checkh(e.next(), E04);
+      `checkh(e.next(1), E04);
+      //Unsup: `checkh(e.next(2), E01);
+      `checkh(e.prev, E01);
+      `checkh(e.prev(1), E01);
+      //Unsup: `checkh(e.prev(2), E04);
       `checkh(e.num, 3);
       `checks(e.name, "E03");
       //
@@ -59,32 +59,32 @@ module t (/*AUTOARG*/
       end
       else if (cyc==1) begin
 	 `checks(e.name, "E01");
-	 `checkh(e.next, E03); 
-	 `checkh(e.next(1), E03); 
-	 //Unsup: `checkh(e.next(2), E04); 
-	 `checkh(e.prev, E04); 
-	 `checkh(e.prev(1), E04); 
-	 //Unsup: `checkh(e.prev(2), E03); 
+	 `checkh(e.next, E03);
+	 `checkh(e.next(1), E03);
+	 //Unsup: `checkh(e.next(2), E04);
+	 `checkh(e.prev, E04);
+	 `checkh(e.prev(1), E04);
+	 //Unsup: `checkh(e.prev(2), E03);
 	 e <= E03;
       end
       else if (cyc==2) begin
 	 `checks(e.name, "E03");
-	 `checkh(e.next, E04); 
-	 `checkh(e.next(1), E04); 
-	 //Unsup: `checkh(e.next(2), E01); 
-	 `checkh(e.prev, E01); 
-	 `checkh(e.prev(1), E01); 
-	 //Unsup: `checkh(e.prev(2), E04); 
+	 `checkh(e.next, E04);
+	 `checkh(e.next(1), E04);
+	 //Unsup: `checkh(e.next(2), E01);
+	 `checkh(e.prev, E01);
+	 `checkh(e.prev(1), E01);
+	 //Unsup: `checkh(e.prev(2), E04);
 	 e <= E04;
       end
       else if (cyc==3) begin
 	 `checks(e.name, "E04");
-	 `checkh(e.next, E01); 
-	 `checkh(e.next(1), E01); 
-	 //Unsup: `checkh(e.next(2), E03); 
-	 `checkh(e.prev, E03); 
-	 `checkh(e.prev(1), E03); 
-	 //Unsup: `checkh(e.prev(2), E01); 
+	 `checkh(e.next, E01);
+	 `checkh(e.next(1), E01);
+	 //Unsup: `checkh(e.next(2), E03);
+	 `checkh(e.prev, E03);
+	 `checkh(e.prev(1), E03);
+	 //Unsup: `checkh(e.prev(2), E01);
 	 e <= E01;
       end
       else if (cyc==99) begin
diff --git a/test_regress/t/t_for_init_bug.v b/test_regress/t/t_for_init_bug.v
index e9167ee9b..b00eeb2fd 100644
--- a/test_regress/t/t_for_init_bug.v
+++ b/test_regress/t/t_for_init_bug.v
@@ -29,7 +29,7 @@ module t (/*AUTOARG*/
       //Bit zero is always enabled
       priority_mask[0]=1'b0;
    end
-   
+
 endmodule
 
 // Local Variables:
diff --git a/test_regress/t/t_func_begin2.v b/test_regress/t/t_func_begin2.v
index 01aeb9d43..57f5f3c02 100644
--- a/test_regress/t/t_func_begin2.v
+++ b/test_regress/t/t_func_begin2.v
@@ -4,7 +4,7 @@
 // without warranty, 2012 by Wilson Snyder.
 
 module init;
-   
+
    task t1;
       reg 		 ba,bb,bc,bd,be,bf,bg,bh,bi,bj,bk,bl,bm,bn,bo,bp,bq,br,bs,bt,bu,bv,bw,bx,by,bz;
       reg 		 ca,cb,cc,cd,ce,cf,cg,ch,ci,cj,ck,cl,cm,cn,co,cp,cq,cr,cs,ct,cu,cv,cw,cx,cy,cz;
diff --git a/test_regress/t/t_func_const_bad.v b/test_regress/t/t_func_const_bad.v
index d96750098..bdafacbc4 100644
--- a/test_regress/t/t_func_const_bad.v
+++ b/test_regress/t/t_func_const_bad.v
@@ -15,7 +15,7 @@ module t;
 
    // Speced Illegal: void
 
-   // Speced Illegal: dotted 
+   // Speced Illegal: dotted
    localparam EIGHT = 8;
    localparam B2 = f_bad_dotted(2);
    function integer f_bad_dotted(input [31:0] a);
diff --git a/test_regress/t/t_func_noinl.v b/test_regress/t/t_func_noinl.v
index 0f552efe8..4b6e40e96 100644
--- a/test_regress/t/t_func_noinl.v
+++ b/test_regress/t/t_func_noinl.v
@@ -89,12 +89,12 @@ module Test (/*AUTOARG*/
 
 	 for (i = 0; i < 32; i = i + 1)
 	   if (var2[i]) begin
-	      product1 = { {31*2+1-32{1'b0}}, var1} << i; 
+	      product1 = { {31*2+1-32{1'b0}}, var1} << i;
 	      product2 = product2 ^ product1;
 	   end
 	 no_inline_function = 0;
 
-	 for (i= 0; i < 31; i = i + 1 ) 
+	 for (i= 0; i < 31; i = i + 1 )
 	   no_inline_function[i+1] = no_inline_function[i] ^ product2[i] ^ var1[i];
       end
    endfunction
diff --git a/test_regress/t/t_func_wide_out_bad.v b/test_regress/t/t_func_wide_out_bad.v
index c23808845..1044b59b4 100644
--- a/test_regress/t/t_func_wide_out_bad.v
+++ b/test_regress/t/t_func_wide_out_bad.v
@@ -7,9 +7,9 @@ module t ();
 
    parameter MSG_PORT_WIDTH = 4350;
    localparam PAYLOAD_MAX_BITS = 4352;
-   
+
    reg [MSG_PORT_WIDTH-1:0] 	msg;
-   
+
    initial begin
       // Operator TASKREF 'func' expects 4352 bits on the Function Argument, but Function Argument's VARREF 'msg' generates 4350 bits.
       // verilator lint_off WIDTH
diff --git a/test_regress/t/t_gate_unsup.v b/test_regress/t/t_gate_unsup.v
index e48be1f9d..2e78fd2a1 100644
--- a/test_regress/t/t_gate_unsup.v
+++ b/test_regress/t/t_gate_unsup.v
@@ -17,7 +17,7 @@ module t (/*AUTOARG*/);
    rpmos     (rp0, d, en);
 
    rtran     (rt0, d);
-   tran      (tr0, d); 
+   tran      (tr0, d);
 
    rtranif0  (r00, d, en);
    rtranif1  (r10, d, en);
diff --git a/test_regress/t/t_gen_inc.v b/test_regress/t/t_gen_inc.v
index faa4d50d2..2a9884f8d 100644
--- a/test_regress/t/t_gen_inc.v
+++ b/test_regress/t/t_gen_inc.v
@@ -110,5 +110,5 @@ module t (/*AUTOARG*/
 	 $finish;
       end
    end
-      
+
 endmodule
diff --git a/test_regress/t/t_gen_missing.v b/test_regress/t/t_gen_missing.v
index 02ef3665f..a491964c7 100644
--- a/test_regress/t/t_gen_missing.v
+++ b/test_regress/t/t_gen_missing.v
@@ -22,7 +22,7 @@ module foobar
      FOO_TYPE = 1
      )
     (
-    input wire[FOO_NUM-1:0] foo, 
+    input wire[FOO_NUM-1:0] foo,
     output wire[FOO_NUM-1:0] bar);
 
 
@@ -51,7 +51,7 @@ endmodule
 module foo0(input wire x, output wire y);
 
    assign y = ~x;
-   
+
    initial begin
       $write("*-* All Finished *-*\n");
       $finish;
diff --git a/test_regress/t/t_inst_array_partial.v b/test_regress/t/t_inst_array_partial.v
index 3ae5a9000..f12601507 100644
--- a/test_regress/t/t_inst_array_partial.v
+++ b/test_regress/t/t_inst_array_partial.v
@@ -79,7 +79,7 @@ module t (/*AUTOARG*/
 	 $finish;
       end
    end
-   
+
 endmodule // t
 
 
@@ -89,5 +89,5 @@ module sub
     output wire       bitout);
 
    assign bitout = (^ twobits) ^ (^ allbits);
-  
+
 endmodule // sub
diff --git a/test_regress/t/t_inst_dtree.v b/test_regress/t/t_inst_dtree.v
index 459bcf261..11cfa9a46 100644
--- a/test_regress/t/t_inst_dtree.v
+++ b/test_regress/t/t_inst_dtree.v
@@ -8,7 +8,7 @@ module t (/*AUTOARG*/
    clk
    );
    input clk;
-   
+
 `ifdef INLINE_A //verilator inline_module
 `else  //verilator no_inline_module
 `endif
diff --git a/test_regress/t/t_inst_signed.v b/test_regress/t/t_inst_signed.v
index acea72eb0..c92c0e3f8 100644
--- a/test_regress/t/t_inst_signed.v
+++ b/test_regress/t/t_inst_signed.v
@@ -14,7 +14,7 @@ module t (/*AUTOARG*/
 
    wire signed [7:0] sgn_wide;
    wire [7:0] 	     unsgn_wide;
-   
+
    // The instantiation will Z extend, not sign extend
    // verilator lint_off WIDTH
    sub sub (.clk,
diff --git a/test_regress/t/t_inst_slice.v b/test_regress/t/t_inst_slice.v
index 397a8d0db..55a4c3594 100644
--- a/test_regress/t/t_inst_slice.v
+++ b/test_regress/t/t_inst_slice.v
@@ -63,7 +63,7 @@ module Test
    output logic [1:0] o [3:0],
    //but this works
    //logic [N-1:0] o
-   input 	[1:0] i);   
+   input 	[1:0] i);
 
    parameter N = 4;
 
diff --git a/test_regress/t/t_lint_blksync_bad.v b/test_regress/t/t_lint_blksync_bad.v
index 423b4a8bc..159b7911e 100644
--- a/test_regress/t/t_lint_blksync_bad.v
+++ b/test_regress/t/t_lint_blksync_bad.v
@@ -20,14 +20,14 @@ module t (/*AUTOARG*/
    reg 	 combo_nblk;
 
    always @(posedge clk) begin
-      sync_blk = 1'b1; 
+      sync_blk = 1'b1;
       sync_blk2 = 1'b1;   // Only warn once per block
-      sync_nblk <= 1'b1; 
+      sync_nblk <= 1'b1;
    end
 
    always @* begin
-      combo_blk = 1'b1; 
-      combo_nblk <= 1'b1; 
+      combo_blk = 1'b1;
+      combo_nblk <= 1'b1;
    end
 
    always @(posedge clk) begin
diff --git a/test_regress/t/t_lint_blksync_loop.v b/test_regress/t/t_lint_blksync_loop.v
index c7977a2bc..2bf1ef4c7 100644
--- a/test_regress/t/t_lint_blksync_loop.v
+++ b/test_regress/t/t_lint_blksync_loop.v
@@ -26,7 +26,7 @@ module t (/*AUTOARG*/
    // End of automatics
 
    reg_1r1w #(.WIDTH(32), .DEPTH(256), .ADRWID(8))
-   sub 
+   sub
      (/*AUTOINST*/
       // Outputs
       .data_out				(data_out[31:0]),
diff --git a/test_regress/t/t_lint_inherit.v b/test_regress/t/t_lint_inherit.v
index 24757da6a..1d30cf928 100644
--- a/test_regress/t/t_lint_inherit.v
+++ b/test_regress/t/t_lint_inherit.v
@@ -29,7 +29,7 @@ module m1
    input d,
    output wire [1:0] q
    );
-   
+
    m2 m2 (/*AUTOINST*/
 	  // Outputs
 	  .q				(q[1:0]),
@@ -47,7 +47,7 @@ module m2
    output reg [1:0] q
    // verilator lint_on UNOPT
    );
-   
+
    always @* begin
       q[1] = d;
    end
diff --git a/test_regress/t/t_lint_multidriven_bad.v b/test_regress/t/t_lint_multidriven_bad.v
index 4806102f8..46748db64 100644
--- a/test_regress/t/t_lint_multidriven_bad.v
+++ b/test_regress/t/t_lint_multidriven_bad.v
@@ -33,5 +33,5 @@ module t (/*AUTOARG*/
    always @(negedge clk) begin
       out2[15:8] <= d0;
    end
-   
+
 endmodule
diff --git a/test_regress/t/t_lint_unsup_deassign.v b/test_regress/t/t_lint_unsup_deassign.v
index f2bca1540..c931e6213 100644
--- a/test_regress/t/t_lint_unsup_deassign.v
+++ b/test_regress/t/t_lint_unsup_deassign.v
@@ -9,7 +9,7 @@ module t
    );
 
    integer q;
-   
+
    always @(*)
      if (rst)
        assign q = 0;
diff --git a/test_regress/t/t_lint_unsup_mixed.v b/test_regress/t/t_lint_unsup_mixed.v
index 58c66c8e7..779b0396f 100644
--- a/test_regress/t/t_lint_unsup_mixed.v
+++ b/test_regress/t/t_lint_unsup_mixed.v
@@ -11,13 +11,13 @@ module t
    );
 
    integer q;
-   
+
    // bug1120
    always @ (a or posedge clk)
      begin
 	if (a)
           q = 0;
-	else 
+	else
           q = q + 1;
      end
 
diff --git a/test_regress/t/t_lint_unused_bad.v b/test_regress/t/t_lint_unused_bad.v
index 9cdacf34b..1c17495a7 100644
--- a/test_regress/t/t_lint_unused_bad.v
+++ b/test_regress/t/t_lint_unused_bad.v
@@ -21,7 +21,7 @@ module sub;
    assign udrb2[15] = 0;
    assign udrb2[12] = 0;
    assign udrb2[10] = 0;
-   
+
    wire       unu3;  // Totally unused
 
    wire [3:0] mixed;  // [3] unused & undr, [2] unused, [1] undr, [0] ok
diff --git a/test_regress/t/t_math_msvc_64.v b/test_regress/t/t_math_msvc_64.v
index 2a705bec2..e5052f47d 100644
--- a/test_regress/t/t_math_msvc_64.v
+++ b/test_regress/t/t_math_msvc_64.v
@@ -10,8 +10,8 @@ module t (/*AUTOARG*/
    input clk;
 
    integer 	cyc=0;
-   
-   reg [89:0]	in;   
+
+   reg [89:0]	in;
 
    /*AUTOWIRE*/
    // Beginning of automatic wires (for undeclared instantiated-module outputs)
@@ -19,7 +19,7 @@ module t (/*AUTOARG*/
    wire [44:0] 		line0;
    wire [44:0] 		line1;
    // End of automatics
-   
+
    Test test (/*AUTOINST*/
 	      // Outputs
 	      .out			(out[89:0]),
@@ -28,15 +28,15 @@ module t (/*AUTOARG*/
 	      // Inputs
 	      .clk			(clk),
 	      .in			(in[89:0]));
-  
+
    // Test loop
-   always @ (posedge clk) begin   
+   always @ (posedge clk) begin
 `ifdef TEST_VERBOSE
       $write("[%0t] cyc==%0d in=%x out=%x\n",$time, cyc, in, out);
 `endif
-      cyc <= cyc + 1;      
+      cyc <= cyc + 1;
       if (cyc==0) begin
-	 // Setup	 
+	 // Setup
 	 in <= 90'h3FFFFFFFFFFFFFFFFFFFFFF;
       end
       else if (cyc==10) begin
@@ -48,7 +48,7 @@ module t (/*AUTOARG*/
 	   $write("*-* Failed!! *-*\n");
 	    $finish;
 	 end
-      end      
+      end
    end
 
 endmodule
@@ -61,12 +61,12 @@ module Test (/*AUTOARG*/
    );
 
    input clk;
-   input [89:0] in;   
-   
+   input [89:0] in;
+
    output reg [44:0]	line0;
-   output reg [44:0]	line1;   
-   output reg [89:0]	out;      
-   
+   output reg [44:0]	line1;
+   output reg [89:0]	out;
+
    assign  {line0,line1} = in;
    always @(posedge clk) begin
       out <= {line0,line1};
diff --git a/test_regress/t/t_math_pow5.v b/test_regress/t/t_math_pow5.v
index e56ea8045..1224836c8 100644
--- a/test_regress/t/t_math_pow5.v
+++ b/test_regress/t/t_math_pow5.v
@@ -26,7 +26,7 @@ module t (/*AUTOARG*/
       qs = 68'she_12345678_9abcdef0 ** 68'sh5_6789abcd_ef012345;
       if (qs != 68'h0) $stop;
    end
-   
+
    reg [67:0] left;
    reg [67:0] right;
 
diff --git a/test_regress/t/t_math_real.v b/test_regress/t/t_math_real.v
index 563ba223a..a376b7768 100644
--- a/test_regress/t/t_math_real.v
+++ b/test_regress/t/t_math_real.v
@@ -49,7 +49,7 @@ module t (/*AUTOARG*/
       if (((1.5)/(1.25)) != 1.2) $stop;
       //
       if (((1.5)==(2)) != 1'b0) $stop;  // note 2 becomes real 2.0
-      if (((1.5)!=(2)) != 1'b1) $stop; 
+      if (((1.5)!=(2)) != 1'b1) $stop;
       if (((1.5)> (2)) != 1'b0) $stop;
       if (((1.5)>=(2)) != 1'b0) $stop;
       if (((1.5)< (2)) != 1'b1) $stop;
@@ -124,7 +124,7 @@ module t (/*AUTOARG*/
 	 //
 	 r = $itor(cyc);
 	 if ((r==50.0) != (cyc==50)) $stop;
-	 if ((r!=50.0) != (cyc!=50)) $stop; 
+	 if ((r!=50.0) != (cyc!=50)) $stop;
 	 if ((r> 50.0) != (cyc> 50)) $stop;
 	 if ((r>=50.0) != (cyc>=50)) $stop;
 	 if ((r< 50.0) != (cyc< 50)) $stop;
diff --git a/test_regress/t/t_math_sign_extend.v b/test_regress/t/t_math_sign_extend.v
index 31084942d..42d5d9a97 100644
--- a/test_regress/t/t_math_sign_extend.v
+++ b/test_regress/t/t_math_sign_extend.v
@@ -1,7 +1,7 @@
 // DESCRIPTION: Verilator: Verilog Test module
 //
 //  This test demonstrates an issue with sign extension.
-//  Assigning to localparms larger than 32 bits broke in 3.862 
+//  Assigning to localparms larger than 32 bits broke in 3.862
 //
 // This file ONLY is placed into the Public Domain, for any use,
 // without warranty, 2015 by Mike Thyer.
@@ -12,7 +12,7 @@ module t (/*AUTOARG*/
    );
    input clk;
 
-   
+
    localparam [ 0:0] one1_lp = 1;
    localparam [ 1:0] one2_lp = 1;
    localparam [ 2:0] one3_lp = 1;
@@ -47,47 +47,47 @@ module t (/*AUTOARG*/
    localparam [67:0] one68_lp = 1;
    localparam [68:0] one69_lp = 1;
    localparam [69:0] one70_lp = 1;
-   
+
    bit all_ok = 1;
 
    initial begin
 `ifdef TEST_VERBOSE
-     $display("one1_lp : %x %d", one1_lp, one1_lp==1); 
-     $display("one2_lp : %x %d", one2_lp, one2_lp==1); 
-     $display("one3_lp : %x %d", one3_lp, one3_lp==1); 
-     $display("one4_lp : %x %d", one4_lp, one4_lp==1); 
-     $display("one5_lp : %x %d", one5_lp, one5_lp==1); 
-     $display("one6_lp : %x %d", one6_lp, one6_lp==1); 
-     $display("one7_lp : %x %d", one7_lp, one7_lp==1); 
-     $display("one8_lp : %x %d", one8_lp, one8_lp==1); 
-     $display("one9_lp : %x %d", one9_lp, one9_lp==1); 
-     $display("one10_lp: %x %d", one10_lp, one10_lp==1); 
-     $display("one20_lp: %x %d", one20_lp, one20_lp==1); 
-     $display("one30_lp: %x %d", one30_lp, one30_lp==1); 
-     $display("one31_lp: %x %d", one31_lp, one31_lp==1); 
-     $display("one32_lp: %x %d", one32_lp, one32_lp==1); 
-     $display("one33_lp: %x %d", one33_lp, one33_lp==1); 
-     $display("one34_lp: %x %d", one34_lp, one34_lp==1); 
-     $display("one35_lp: %x %d", one35_lp, one35_lp==1); 
-     $display("one36_lp: %x %d", one36_lp, one36_lp==1); 
-     $display("one37_lp: %x %d", one37_lp, one37_lp==1); 
-     $display("one38_lp: %x %d", one38_lp, one38_lp==1); 
-     $display("one39_lp: %x %d", one39_lp, one39_lp==1); 
-     $display("one40_lp: %x %d", one40_lp, one40_lp==1); 
-     $display("one50_lp: %x %d", one50_lp, one50_lp==1); 
-     $display("one60_lp: %x %d", one60_lp, one60_lp==1); 
-     $display("one61_lp: %x %d", one61_lp, one61_lp==1); 
-     $display("one62_lp: %x %d", one62_lp, one62_lp==1); 
-     $display("one63_lp: %x %d", one63_lp, one63_lp==1); 
-     $display("one64_lp: %x %d", one64_lp, one64_lp==1); 
-     $display("one65_lp: %x %d", one65_lp, one65_lp==1); 
-     $display("one66_lp: %x %d", one66_lp, one66_lp==1); 
-     $display("one67_lp: %x %d", one67_lp, one67_lp==1); 
-     $display("one68_lp: %x %d", one68_lp, one68_lp==1); 
-     $display("one69_lp: %x %d", one69_lp, one69_lp==1); 
+     $display("one1_lp : %x %d", one1_lp, one1_lp==1);
+     $display("one2_lp : %x %d", one2_lp, one2_lp==1);
+     $display("one3_lp : %x %d", one3_lp, one3_lp==1);
+     $display("one4_lp : %x %d", one4_lp, one4_lp==1);
+     $display("one5_lp : %x %d", one5_lp, one5_lp==1);
+     $display("one6_lp : %x %d", one6_lp, one6_lp==1);
+     $display("one7_lp : %x %d", one7_lp, one7_lp==1);
+     $display("one8_lp : %x %d", one8_lp, one8_lp==1);
+     $display("one9_lp : %x %d", one9_lp, one9_lp==1);
+     $display("one10_lp: %x %d", one10_lp, one10_lp==1);
+     $display("one20_lp: %x %d", one20_lp, one20_lp==1);
+     $display("one30_lp: %x %d", one30_lp, one30_lp==1);
+     $display("one31_lp: %x %d", one31_lp, one31_lp==1);
+     $display("one32_lp: %x %d", one32_lp, one32_lp==1);
+     $display("one33_lp: %x %d", one33_lp, one33_lp==1);
+     $display("one34_lp: %x %d", one34_lp, one34_lp==1);
+     $display("one35_lp: %x %d", one35_lp, one35_lp==1);
+     $display("one36_lp: %x %d", one36_lp, one36_lp==1);
+     $display("one37_lp: %x %d", one37_lp, one37_lp==1);
+     $display("one38_lp: %x %d", one38_lp, one38_lp==1);
+     $display("one39_lp: %x %d", one39_lp, one39_lp==1);
+     $display("one40_lp: %x %d", one40_lp, one40_lp==1);
+     $display("one50_lp: %x %d", one50_lp, one50_lp==1);
+     $display("one60_lp: %x %d", one60_lp, one60_lp==1);
+     $display("one61_lp: %x %d", one61_lp, one61_lp==1);
+     $display("one62_lp: %x %d", one62_lp, one62_lp==1);
+     $display("one63_lp: %x %d", one63_lp, one63_lp==1);
+     $display("one64_lp: %x %d", one64_lp, one64_lp==1);
+     $display("one65_lp: %x %d", one65_lp, one65_lp==1);
+     $display("one66_lp: %x %d", one66_lp, one66_lp==1);
+     $display("one67_lp: %x %d", one67_lp, one67_lp==1);
+     $display("one68_lp: %x %d", one68_lp, one68_lp==1);
+     $display("one69_lp: %x %d", one69_lp, one69_lp==1);
      $display("one70_lp: %x %d", one70_lp, one70_lp==1);
 `endif
-  
+
      all_ok &= one1_lp  == 1;
      all_ok &= one2_lp  == 1;
      all_ok &= one3_lp  == 1;
@@ -122,11 +122,11 @@ module t (/*AUTOARG*/
      all_ok &= one68_lp == 1;
      all_ok &= one69_lp == 1;
      all_ok &= one70_lp == 1;
-     
+
      if (!all_ok) $stop;
      $write("*-* All Finished *-*\n");
      $finish;
-     
+
    end
 endmodule
 
diff --git a/test_regress/t/t_mem_multi_io3.v b/test_regress/t/t_mem_multi_io3.v
index e2d82667f..76878fb69 100644
--- a/test_regress/t/t_mem_multi_io3.v
+++ b/test_regress/t/t_mem_multi_io3.v
@@ -39,10 +39,10 @@ module testio
    );
    logic signed [3:0] [35:0] 		ar2d_out_pre;
 
-   always_comb ar2d_out_pre[0][35:0] = {arr3d_in[0][0][8:0], arr3d_in[0][1][8:0], arr3d_in[0][2][8:0], arr3d_in[0][3][8:0]}; 
-   always_comb ar2d_out_pre[0][35:0] = {arr3d_in[0][0][8:0], arr3d_in[0][1][8:0], arr3d_in[0][2][8:0], arr3d_in[0][3][8:0]}; 
-   always_comb ar2d_out_pre[0][35:0] = {arr3d_in[0][0][8:0], arr3d_in[0][1][8:0], arr3d_in[0][2][8:0], arr3d_in[0][3][8:0]}; 
-   always_comb ar2d_out_pre[0][35:0] = {arr3d_in[0][0][8:0], arr3d_in[0][1][8:0], arr3d_in[0][2][8:0], arr3d_in[0][3][8:0]}; 
+   always_comb ar2d_out_pre[0][35:0] = {arr3d_in[0][0][8:0], arr3d_in[0][1][8:0], arr3d_in[0][2][8:0], arr3d_in[0][3][8:0]};
+   always_comb ar2d_out_pre[0][35:0] = {arr3d_in[0][0][8:0], arr3d_in[0][1][8:0], arr3d_in[0][2][8:0], arr3d_in[0][3][8:0]};
+   always_comb ar2d_out_pre[0][35:0] = {arr3d_in[0][0][8:0], arr3d_in[0][1][8:0], arr3d_in[0][2][8:0], arr3d_in[0][3][8:0]};
+   always_comb ar2d_out_pre[0][35:0] = {arr3d_in[0][0][8:0], arr3d_in[0][1][8:0], arr3d_in[0][2][8:0], arr3d_in[0][3][8:0]};
 
    always_ff @(posedge clk) begin
       if (clk)
diff --git a/test_regress/t/t_mem_slice_conc_bad.v b/test_regress/t/t_mem_slice_conc_bad.v
index 180ed028d..214fd647e 100644
--- a/test_regress/t/t_mem_slice_conc_bad.v
+++ b/test_regress/t/t_mem_slice_conc_bad.v
@@ -3,7 +3,7 @@
 // This file ONLY is placed into the Public Domain, for any use,
 // without warranty, 2011 by Wilson Snyder.
 //
-// bug354 
+// bug354
 
 typedef logic [5:0]  data_t;
 
diff --git a/test_regress/t/t_mem_twoedge.v b/test_regress/t/t_mem_twoedge.v
index c16fc825b..69740401e 100644
--- a/test_regress/t/t_mem_twoedge.v
+++ b/test_regress/t/t_mem_twoedge.v
@@ -113,5 +113,5 @@ module Test (/*AUTOARG*/
    end
 
    assign out = {mem[3],mem[2],mem[1],mem[0]};
-   
+
 endmodule
diff --git a/test_regress/t/t_mod_recurse.v b/test_regress/t/t_mod_recurse.v
index 9de45a499..3cef4ff5d 100644
--- a/test_regress/t/t_mod_recurse.v
+++ b/test_regress/t/t_mod_recurse.v
@@ -20,7 +20,7 @@ module t (/*AUTOARG*/
 
    wire         valid;
    wire [3-1:0] value;
-   
+
    PriorityChoice #(.OCODEWIDTH(3))
    pe (.out(valid), .outN(value[2:0]), .tripline(tripline));
 
@@ -62,7 +62,7 @@ module PriorityChoice (out, outN, tripline);
    parameter OCODEWIDTH = 1;
    localparam CODEWIDTH=OCODEWIDTH-1;
    localparam SCODEWIDTH= (CODEWIDTH<1) ? 1 : CODEWIDTH;
-   
+
    output reg             out;
    output reg [OCODEWIDTH-1:0] outN;
    input wire [(1<<OCODEWIDTH)-1:0] tripline;
@@ -70,12 +70,12 @@ module PriorityChoice (out, outN, tripline);
    wire [SCODEWIDTH-1:0] 	    leftN;
    wire 			    right;
    wire [SCODEWIDTH-1:0] 	    rightN;
-   
+
    generate
       if(OCODEWIDTH==1) begin
 	 assign left = tripline[1];
 	 assign right = tripline[0];
-	 
+
 	 always @(*) begin
 	    out  <= left || right ;
 	    if(right) begin outN <= {1'b0}; end
diff --git a/test_regress/t/t_order_multidriven.v b/test_regress/t/t_order_multidriven.v
index 1a2ff5961..d3202dfe6 100644
--- a/test_regress/t/t_order_multidriven.v
+++ b/test_regress/t/t_order_multidriven.v
@@ -6,7 +6,7 @@
 //With MULTI_CLK defined shows bug, without it is hidden
 `define MULTI_CLK
 
-//bug634 
+//bug634
 
 module t (
     input                   i_clk_wr,
diff --git a/test_regress/t/t_order_quad.v b/test_regress/t/t_order_quad.v
index 37ede648e..60635c549 100644
--- a/test_regress/t/t_order_quad.v
+++ b/test_regress/t/t_order_quad.v
@@ -12,5 +12,5 @@ module t(a0, y);
    assign y[30] = 0;
    // verilator lint_off UNOPTFLAT
    assign { y[44:41], y[39:31], y[29:0] } = { 6'b000000, a0, 7'b0000000, y[40], y[30], y[30], y[30], y[30], 21'b000000000000000000000 };
-   
+
 endmodule
diff --git a/test_regress/t/t_package.v b/test_regress/t/t_package.v
index f7b0892e2..3273062c2 100644
--- a/test_regress/t/t_package.v
+++ b/test_regress/t/t_package.v
@@ -34,7 +34,7 @@ module t (/*AUTOARG*/
    p::package_type_t vp;
 
    t2 t2 ();
-   
+
    initial begin
       if (unit_plusone(1) !== 2) $stop;
       if ($unit::unit_plusone(1) !== 2) $stop;
diff --git a/test_regress/t/t_package_ddecl.v b/test_regress/t/t_package_ddecl.v
index c0cbb5c1f..310ff2bb3 100644
--- a/test_regress/t/t_package_ddecl.v
+++ b/test_regress/t/t_package_ddecl.v
@@ -28,5 +28,3 @@ module t ();
       $finish;
    end
 endmodule
-
-						
\ No newline at end of file
diff --git a/test_regress/t/t_package_verb.v b/test_regress/t/t_package_verb.v
index 23c0696ea..c2749d712 100644
--- a/test_regress/t/t_package_verb.v
+++ b/test_regress/t/t_package_verb.v
@@ -5,7 +5,7 @@
 
 // bug474
 package verb_pkg;
-   typedef enum int {VERB_I, 
+   typedef enum int {VERB_I,
 		     VERB_W} Verb_t;
    Verb_t  verb = VERB_I;
    string message = " ";
diff --git a/test_regress/t/t_param_mem_attr.v b/test_regress/t/t_param_mem_attr.v
index f2369c1af..0499d4068 100644
--- a/test_regress/t/t_param_mem_attr.v
+++ b/test_regress/t/t_param_mem_attr.v
@@ -21,7 +21,7 @@ module t (/*AUTOARG*/
    );
    input clk;
    wire [71:0] ctrl;
-   wire [7:0] cl;                       // this line is added 
+   wire [7:0] cl;                       // this line is added
 
    memory #(.words(72)) i_memory (.clk (clk));
 
diff --git a/test_regress/t/t_param_value.v b/test_regress/t/t_param_value.v
index a3ffaf618..5aed9defc 100644
--- a/test_regress/t/t_param_value.v
+++ b/test_regress/t/t_param_value.v
@@ -32,13 +32,13 @@ module t (/*AUTOARG*/);
    // bullet 2
    localparam [63:0] B_UNSIGNED = SIGNED;
    `ASSERT($bits(B_UNSIGNED)==64 && B_UNSIGNED > 0);
-   
+
    // bullet 3
    localparam signed C_SIGNED = UNSIGNED;
    `ASSERT($bits(C_SIGNED)==64 && C_SIGNED < 0);
 
    localparam unsigned C_UNSIGNED = SIGNED;
-   `ASSERT($bits(C_UNSIGNED)==64 && C_UNSIGNED > 0); 
+   `ASSERT($bits(C_UNSIGNED)==64 && C_UNSIGNED > 0);
 
    // bullet 4
    // verilator lint_off WIDTH
@@ -48,12 +48,12 @@ module t (/*AUTOARG*/);
 
    // verilator lint_off WIDTH
    localparam unsigned [59:0] D_UNSIGNED = SIGNED;
-   `ASSERT($bits(D_UNSIGNED)==60 && D_UNSIGNED > 0); 
+   `ASSERT($bits(D_UNSIGNED)==60 && D_UNSIGNED > 0);
    // verilator lint_on WIDTH
-  
+
    // bullet 6
    localparam UNSIZED = 23;
-   `ASSERT($bits(UNSIZED)>=32); 
+   `ASSERT($bits(UNSIZED)>=32);
 
    initial begin
       $write("*-* All Finished *-*\n");
diff --git a/test_regress/t/t_param_wide_io.v b/test_regress/t/t_param_wide_io.v
index cf872736e..eaed4c9bd 100644
--- a/test_regress/t/t_param_wide_io.v
+++ b/test_regress/t/t_param_wide_io.v
@@ -9,11 +9,11 @@ module t
   #(
     parameter[96:0] P = 97'h12344321_12344321_12344327
     )
-   (	
+   (
 	input [P&7 - 1:0]  in,
 	output [P&7 - 1:0] out
 	);
-   
+
    wire out = in;
 
 endmodule
diff --git a/test_regress/t/t_pp_dupdef_bad.pl b/test_regress/t/t_pp_dupdef_bad.pl
index 90b7ecf10..5b9766fd1 100755
--- a/test_regress/t/t_pp_dupdef_bad.pl
+++ b/test_regress/t/t_pp_dupdef_bad.pl
@@ -15,9 +15,9 @@ compile (
 	 v_flags2 => ["--lint-only"],
 	 fails=>1,
 	 expect=>
-'%Warning-REDEFMACRO: t/t_pp_dupdef.v:\d+: Redefining existing define: DUP, with different value: barney 
+'%Warning-REDEFMACRO: t/t_pp_dupdef.v:\d+: Redefining existing define: DUP, with different value: barney
 %Warning-REDEFMACRO: Use .* to disable this message.
-%Warning-REDEFMACRO: t/t_pp_dupdef.v:\d+: Previous definition is here, with value: fred 
+%Warning-REDEFMACRO: t/t_pp_dupdef.v:\d+: Previous definition is here, with value: fred
 %Warning-REDEFMACRO: t/t_pp_dupdef.v:\d+: Redefining existing define: DUPP, with different value: .*
 %Warning-REDEFMACRO: t/t_pp_dupdef.v:\d+: Previous definition is here, with value: .*
 %Error: Exiting due to.*',
diff --git a/test_regress/t/t_savable.v b/test_regress/t/t_savable.v
index a98c6878a..6b416cec9 100644
--- a/test_regress/t/t_savable.v
+++ b/test_regress/t/t_savable.v
@@ -73,7 +73,7 @@ module sub (/*AUTOARG*/
 	 if (vec[2][1] !== 32'h0201) $stop;
 	 if (vec[2][2] !== 32'h0202) $stop;
 	 if (r != 1.234) $stop;
-	 $display("%s",s); 
+	 $display("%s",s);
 	 $write("*-* All Finished *-*\n");
 	 $finish;
       end
diff --git a/test_regress/t/t_select_index2.v b/test_regress/t/t_select_index2.v
index 97178fed8..475550c9c 100644
--- a/test_regress/t/t_select_index2.v
+++ b/test_regress/t/t_select_index2.v
@@ -13,7 +13,7 @@ module t (/*AUTOARG*/
    wire [3:0] en;
    wire       sel;
    wire       a;
-   
+
    // bug675
    generate
       genvar  g_k;
@@ -32,5 +32,5 @@ module t (/*AUTOARG*/
            end
         end
    endgenerate
-   
+
 endmodule
diff --git a/test_regress/t/t_select_lhs_oob.v b/test_regress/t/t_select_lhs_oob.v
index 37b4ba3e7..82dc65ab6 100644
--- a/test_regress/t/t_select_lhs_oob.v
+++ b/test_regress/t/t_select_lhs_oob.v
@@ -19,7 +19,7 @@ module t (/*AUTOARG*/
    // Four different test cases for out of bounds
    //	=
    //	<=
-   //   Continuous assigns 
+   //   Continuous assigns
    //	Output pin interconnect (also covers cont assigns)
    // Each with both bit selects and array selects
 
diff --git a/test_regress/t/t_stream.v b/test_regress/t/t_stream.v
index 13250f81d..e41a54af9 100644
--- a/test_regress/t/t_stream.v
+++ b/test_regress/t/t_stream.v
@@ -98,7 +98,7 @@ module t (/*AUTOARG*/
       if (4'({ << 4 {4'b0001}}) != 4'b0001) $stop;
       if (4'({ << 5 {4'b0001}}) != 4'b0001) $stop;
 
-      // case					  
+      // case
       dout32 = { << 3 { 32'b11010111000010100100010010010111 }}; if (dout32 != 32'he92910eb) $stop;
       dout11 = { << 4 { 11'b10010010111 }}; if (dout11 != 11'h3cc) $stop;
    end
diff --git a/test_regress/t/t_struct_pat_width.v b/test_regress/t/t_struct_pat_width.v
index bf7c1e95d..398d1dec8 100644
--- a/test_regress/t/t_struct_pat_width.v
+++ b/test_regress/t/t_struct_pat_width.v
@@ -30,7 +30,7 @@ module t (clk);
       if (param._bar != 3) $stop;
       if (param != 6'b110011) $stop;
       if (meh != 6) $stop;
-      
+
       $write("*-* All Finished *-*\n");
       $finish;
    end
diff --git a/test_regress/t/t_struct_port.v b/test_regress/t/t_struct_port.v
index 18d749bea..3ee634c0e 100644
--- a/test_regress/t/t_struct_port.v
+++ b/test_regress/t/t_struct_port.v
@@ -79,6 +79,6 @@ module Test (
    end
 endmodule
 
-// Local Variables:                                                                                                          
-// verilog-typedef-regexp: "_t$"                                                                                             
-// End:                                                                                                                      
+// Local Variables:
+// verilog-typedef-regexp: "_t$"
+// End:
diff --git a/test_regress/t/t_sv_conditional.v b/test_regress/t/t_sv_conditional.v
index 63119bb97..71f19cd39 100644
--- a/test_regress/t/t_sv_conditional.v
+++ b/test_regress/t/t_sv_conditional.v
@@ -79,7 +79,7 @@ module st3_testbench (/*AUTOARG*/
    logic [47:0]     selected_out;
    integer 	    i;
 
-  
+
    initial begin
       decrementA = 1'b0;
       dual_countA = 1'b0;
@@ -121,7 +121,7 @@ module st3_testbench (/*AUTOARG*/
 	.decrementB                      (decrementB),
 	.dual_countB                     (dual_countB),
 	.cntB_en                         (cntB_en));
-  
+
 
    // Logic to print outputs and then finish.
    always @(posedge clk) begin
@@ -161,7 +161,7 @@ module simple_test_3
 
    // Outputs
    output logic [47:0] selected_out);
-   
+
    // Declarations
    logic [3:0] 	       cntA_reg;       // Registered version of cntA
    logic [3:0] 	       cntB_reg;       // Registered version of cntA
@@ -178,7 +178,7 @@ module simple_test_3
 	.cntA_en			(cntA_en),
 	.clk				(clk),
 	.rst				(rst));
-   
+
    counterB
      counterB_inst
        (/*AUTOINST*/
@@ -190,57 +190,57 @@ module simple_test_3
 	.cntB_en			(cntB_en),
 	.clk				(clk),
 	.rst				(rst));
-   
+
    simple_test_3a
      sta
        (.wide_input_bus        (wide_input_bus),
 	.selector              (cntA_reg),
 	.selected_out          (selected_out[7:0]));
-   
+
    simple_test_3b
      stb
        (.wide_input_bus        (wide_input_bus),
 	.selector              (cntA_reg),
 	.selected_out          (selected_out[15:8]));
-   
+
    simple_test_3c
      stc
        (.wide_input_bus        (wide_input_bus),
 	.selector              (cntB_reg),
 	.selected_out          (selected_out[23:16]));
-   
+
    simple_test_3d
      std
        (.wide_input_bus        (wide_input_bus),
 	.selector              (cntB_reg),
 	.selected_out          (selected_out[31:24]));
-   
+
    simple_test_3e
      ste
        (.wide_input_bus        (wide_input_bus),
 	.selector              (cntB_reg),
 	.selected_out          (selected_out[39:32]));
-   
+
    simple_test_3f
      stf
        (.wide_input_bus        (wide_input_bus),
 	.selector              (cntB_reg),
 	.selected_out          (selected_out[47:40]));
 
-  
+
 endmodule // simple_test_3
 
 
-module counterA 
+module counterA
   (output logic [3:0]          cntA_reg, // Registered version of cntA
    input logic decrementA,               // 0=Up-counting, 1=down-counting
    input logic dual_countA,              // Advance counter by 2 steps at a time
    input logic cntA_en,                  // Enable Counter A
    input logic clk,                      // Clock
    input logic rst);                     // Synchronous reset
-     
-            
-                   
+
+
+
    logic [3:0] cntA;                     // combinational count variable.
 
    // Counter A
@@ -261,17 +261,17 @@ module counterA
         if (cntA_en) begin
            if (decrementA)
              if (dual_countA)
-               //cntA = cntA - 2; 
+               //cntA = cntA - 2;
                cntA -= 2;
              else
-               //cntA = cntA - 1; 
+               //cntA = cntA - 1;
                cntA--;
            else
              if (dual_countA)
                //cntA = cntA + 2;
                cntA += 2;
              else
-               //cntA = cntA + 1; 
+               //cntA = cntA + 1;
                cntA++;
         end // if (cntA_en)
      end
@@ -287,8 +287,8 @@ module counterB
    input logic rst);                     // Synchronous reset
 
    // Counter B - tried to write sequential only, but ended up without
-   // SystemVerilog.  
-  
+   // SystemVerilog.
+
    always_ff @(posedge clk) begin
       if (rst)
         cntB_reg <= 0;
@@ -309,7 +309,7 @@ module counterB
         end
    end // always_ff @
 endmodule
-  
+
 
 // A multiplexor in terms of look-up
 module simple_test_3a
@@ -327,11 +327,11 @@ module simple_test_3a
                      wide_input_bus[selector*8+2],
                      wide_input_bus[selector*8+1],
                      wide_input_bus[selector*8]};
-   
+
 endmodule // simple_test_3a
 
 
-// A multiplexer in terms of standard case      
+// A multiplexer in terms of standard case
 module simple_test_3b
   (input logic [8*16-1:0] wide_input_bus,
    input logic [3:0]  selector,
@@ -357,7 +357,7 @@ module simple_test_3b
         4'he: selected_out = wide_input_bus[119:112];
         4'hf: selected_out = wide_input_bus[127:120];
       endcase // case (selector)
-      
+
    end
 
 endmodule // simple_test_3b
@@ -371,7 +371,7 @@ module simple_test_3c
 
 
    always_comb begin
-      unique case (selector) 
+      unique case (selector)
         4'h0: selected_out = wide_input_bus[  7:  0];
         4'h1: selected_out = wide_input_bus[ 15:  8];
         4'h2: selected_out = wide_input_bus[ 23: 16];
@@ -389,7 +389,7 @@ module simple_test_3c
         4'he: selected_out = wide_input_bus[119:112];
         4'hf: selected_out = wide_input_bus[127:120];
       endcase // case (selector)
-      
+
    end
 
 endmodule // simple_test_3c
@@ -420,7 +420,7 @@ module simple_test_3d
       else if (selector == 4'he) selected_out = wide_input_bus[119:112];
       else if (selector == 4'hf) selected_out = wide_input_bus[127:120];
    end
-   
+
 endmodule // simple_test_3d
 
 
@@ -440,7 +440,7 @@ module simple_test_3e
         selector[3]: selected_out = wide_input_bus[ 71: 64]; // Bit 3 has lowest priority
         default:     selected_out = wide_input_bus[127:120]; // for selector = 0.
       endcase // case (selector)
-      
+
    end
 
 endmodule // simple_test_3e
@@ -456,7 +456,7 @@ module simple_test_3f
    output logic [7:0] selected_out);
 
 
-   always_comb begin      
+   always_comb begin
 /* -----\/----- EXCLUDED -----\/-----
       if ( selector[3:0] inside { 4'b?00?, 4'b1100})      // Matching 0000, 0001, 1000, 1100, 1001
 	// if ( selector[3:2] inside { 2'b?0, selector[1:0]})
diff --git a/test_regress/t/t_tri_gen.v b/test_regress/t/t_tri_gen.v
index ad70726ba..9fa7a3d2c 100644
--- a/test_regress/t/t_tri_gen.v
+++ b/test_regress/t/t_tri_gen.v
@@ -36,8 +36,8 @@ module updown #(parameter UP=0)
    endgenerate
 endmodule
 
-module t_up (inout tri1 z); 
+module t_up (inout tri1 z);
 endmodule
 
-module t_down (inout tri0 z); 
+module t_down (inout tri0 z);
 endmodule
diff --git a/test_regress/t/t_tri_ifbegin.v b/test_regress/t/t_tri_ifbegin.v
index 21f1f104b..899d051df 100644
--- a/test_regress/t/t_tri_ifbegin.v
+++ b/test_regress/t/t_tri_ifbegin.v
@@ -45,7 +45,7 @@ module sub (/*AUTOARG*/
             if (DIFFERENTIAL)
               assign pad_io_l = sig_l_r;
          end
-      end 
+      end
    endgenerate
 
 endmodule
diff --git a/test_regress/t/t_tri_pull2_bad.v b/test_regress/t/t_tri_pull2_bad.v
index 4bb328f84..26080aeae 100644
--- a/test_regress/t/t_tri_pull2_bad.v
+++ b/test_regress/t/t_tri_pull2_bad.v
@@ -5,13 +5,13 @@ module t (clk);
    input clk;
 
    wire  A;
-   
+
    pullup p1(A);
 
    child child(/*AUTOINST*/
 	       // Inouts
 	       .A			(A));
-   
+
 endmodule
 
 module child(inout A);
diff --git a/test_regress/t/t_tri_pull_bad.v b/test_regress/t/t_tri_pull_bad.v
index 08ce012a1..8241a7a3b 100644
--- a/test_regress/t/t_tri_pull_bad.v
+++ b/test_regress/t/t_tri_pull_bad.v
@@ -5,7 +5,7 @@ module t (clk);
    input clk;
 
    wire  A;
-   
+
    pullup p1(A);
    pulldown p2(A);
 
diff --git a/test_regress/t/t_typedef_signed.v b/test_regress/t/t_typedef_signed.v
index a0245942c..2432f94a5 100644
--- a/test_regress/t/t_typedef_signed.v
+++ b/test_regress/t/t_typedef_signed.v
@@ -76,7 +76,7 @@ module Test( output logic o,
       integer  k;
 
       rc_d[1] <= rc;
-      
+
       for( k=2; k<RATIO+1; k++ ) begin
          rc_d[k] <= rc_d[k-1];
       end
diff --git a/test_regress/t/t_unopt_bound.v b/test_regress/t/t_unopt_bound.v
index c2aba4f93..ba60499c1 100644
--- a/test_regress/t/t_unopt_bound.v
+++ b/test_regress/t/t_unopt_bound.v
@@ -3,7 +3,7 @@
 // This file ONLY is placed into the Public Domain, for any use,
 // without warranty, 2013 by Jue Xu.
 
-// bug630 
+// bug630
 
 module t ( clk, out );
    input clk;
diff --git a/test_regress/t/t_var_assign_landr.v b/test_regress/t/t_var_assign_landr.v
index e03dedba1..28323e2e2 100644
--- a/test_regress/t/t_var_assign_landr.v
+++ b/test_regress/t/t_var_assign_landr.v
@@ -82,7 +82,7 @@ module Test (/*AUTOARG*/
    input [127:0] in;
    output logic [127:0] o1;
    output logic [127:0] o2;
-   
+
    always_comb begin: b_test
       logic [127:0] tmpp;
       logic [127:0] tmp;
diff --git a/test_regress/t/t_var_in_assign.v b/test_regress/t/t_var_in_assign.v
index 894a7e964..ed7475a32 100644
--- a/test_regress/t/t_var_in_assign.v
+++ b/test_regress/t/t_var_in_assign.v
@@ -49,7 +49,7 @@ module t (/*AUTOARG*/
    function integer assignin(input integer i);
       i = 2;
       assignin = i;
-   endfunction 
+   endfunction
 
 endmodule
 
diff --git a/test_regress/t/t_var_pinsizes.v b/test_regress/t/t_var_pinsizes.v
index f6ad839f5..89aa944ff 100644
--- a/test_regress/t/t_var_pinsizes.v
+++ b/test_regress/t/t_var_pinsizes.v
@@ -25,7 +25,6 @@ module t (/*AUTOARG*/
    input [512:0] i513;
    input 	 i1a2 [1:0];
    input [93:0]  i94a3 [2:0];
-   
 
    output 	  o1;
    output [7:0]   o8;
diff --git a/test_regress/t/t_var_static.v b/test_regress/t/t_var_static.v
index 2e38c75b2..ad8f2a825 100644
--- a/test_regress/t/t_var_static.v
+++ b/test_regress/t/t_var_static.v
@@ -19,7 +19,7 @@ module t (/*AUTOARG*/
    function int f_no_au ();
       automatic int st = 2; st++; return st;
    endfunction
-   
+
    function static int f_st_no ();
       int st = 2; st++; return st;
    endfunction
@@ -39,7 +39,7 @@ module t (/*AUTOARG*/
    function automatic int f_au_au ();
       automatic int st = 2; st++; return st;
    endfunction
- 
+
    initial begin
       if (f_no_no() != 3) $stop;
       if (f_no_no() !=   4) $stop;
diff --git a/test_regress/t/t_var_tieout.v b/test_regress/t/t_var_tieout.v
index f7f448dc4..efdf8f2e2 100644
--- a/test_regress/t/t_var_tieout.v
+++ b/test_regress/t/t_var_tieout.v
@@ -2,7 +2,7 @@
 // This file ONLY is placed into the Public Domain, for any use,
 // without warranty, 2010 by Wilson Snyder.
 
-// bug291 
+// bug291
 module t (/*AUTOARG*/
    // Inputs
    clk
diff --git a/test_regress/t/t_vpi_var.v b/test_regress/t/t_vpi_var.v
index 624f3e0b4..dfa61ec48 100644
--- a/test_regress/t/t_vpi_var.v
+++ b/test_regress/t/t_vpi_var.v
@@ -38,7 +38,7 @@ extern "C" int mon_check();
    reg [31:0] 	   text_word    /*verilator public_flat_rw @(posedge clk) */;
    reg [63:0] 	   text_long    /*verilator public_flat_rw @(posedge clk) */;
    reg [511:0] 	   text         /*verilator public_flat_rw @(posedge clk) */;
-   
+
    integer 	  status;
 
    sub sub();
diff --git a/test_verilated/vgen.pl b/test_verilated/vgen.pl
index 4c97a065c..4039bc523 100755
--- a/test_verilated/vgen.pl
+++ b/test_verilated/vgen.pl
@@ -13,6 +13,7 @@ use vars qw ($Debug);
 
 our @Orig_ARGV = @ARGV;
 our $Rerun_Args = $0." ".join(' ',@Orig_ARGV);
+$Rerun_Args =~ s/\s+$//;
 
 use vars qw (@Blocks
 	     %Vars