Mario1159/verilator
1
0
Fork 0
forked from github/verilator
Code Pull Requests Releases 1 Activity

In XML, show pinIndex information (#2877).

Browse Source
This commit is contained in:
Wilson Snyder 2021-06-19 13:41:19 -04:00
parent eebda248c7
commit c11cd18491
14 changed files with 58 additions and 52 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
Changes
View File

@ -22,6 +22,7 @@ Verilator 4.205 devel
* Remove deprecated --no-relative-cfuncs option (#3024). [Geza Lore]
* Merge const static data globally into a new constant pool (#3013). [Geza Lore]
* Allow configure override of AR program (#2999). [ahouska]
* In XML, show pinIndex information (#2877). [errae233]
* Fix error on unsupported recursive functions (#2957). [Trefor Southwell]

9
src/V3AstNodes.h
View File

@ -1889,6 +1889,10 @@ private:
VDirection m_direction; // Direction input/output etc
VDirection m_declDirection; // Declared direction input/output etc
AstBasicDTypeKwd m_declKwd; // Keyword at declaration time
VLifetime m_lifetime; // Lifetime
VVarAttrClocker m_attrClocker;
MTaskIdSet m_mtaskIds; // MTaskID's that read or write this var
int m_pinNum = 0; // For XML, if non-zero the connection pin number
bool m_ansi : 1; // ANSI port list variable (for dedup check)
bool m_declTyped : 1; // Declared as type (for dedup check)
bool m_tristate : 1; // Inout or triwire or trireg
@ -1925,9 +1929,6 @@ private:
bool m_overridenParam : 1; // Overridden parameter by #(...) or defparam
bool m_trace : 1; // Trace this variable
bool m_isLatched : 1; // Not assigned in all control paths of combo always
VLifetime m_lifetime; // Lifetime
VVarAttrClocker m_attrClocker;
MTaskIdSet m_mtaskIds; // MTaskID's that read or write this var
void init() {
m_ansi = false;
@ -2226,6 +2227,8 @@ public:
void addProducingMTaskId(int id) { m_mtaskIds.insert(id); }
void addConsumingMTaskId(int id) { m_mtaskIds.insert(id); }
const MTaskIdSet& mtaskIds() const { return m_mtaskIds; }
void pinNum(int id) { m_pinNum = id; }
int pinNum() const { return m_pinNum; }
};
class AstDefParam final : public AstNode {

1
src/V3EmitXml.cpp
View File

@ -136,6 +136,7 @@ class EmitXmlFileVisitor final : public AstNVisitor {
if (nodep->isIO()) {
puts(" dir=");
putsQuoted(kw);
if (nodep->pinNum() != 0) puts(" pinIndex=\"" + cvtToStr(nodep->pinNum()) + "\"");
puts(" vartype=");
putsQuoted(!vt.empty() ? vt : typ == AstVarType::PORT ? "port" : "unknown");
} else {

1
src/V3LinkDot.cpp
View File

@ -1438,6 +1438,7 @@ private:
"__pinNumber" + cvtToStr(nodep->pinNum()), refp,
nullptr /*classOrPackagep*/);
symp->exported(false);
refp->pinNum(nodep->pinNum());
}
// Ports not needed any more
VL_DO_DANGLING(nodep->unlinkFrBack()->deleteTree(), nodep);

6
test_regress/t/t_clk_concat.pl
View File

@ -17,9 +17,9 @@ compile(
);
if ($Self->{vlt_all}) {
file_grep("$out_filename", qr/\<var fl="d74" loc=".*?" name="clk0" dtype_id="1" dir="input" vartype="logic" origName="clk0" clocker="true" public="true"\/\>/i);
file_grep("$out_filename", qr/\<var fl="d75" loc=".*?" name="clk1" dtype_id="1" dir="input" vartype="logic" origName="clk1" clocker="true" public="true"\/\>/i);
file_grep("$out_filename", qr/\<var fl="d76" loc=".*?" name="clk2" dtype_id="1" dir="input" vartype="logic" origName="clk2" clocker="true" public="true"\/\>/i);
file_grep("$out_filename", qr/\<var fl="d74" loc=".*?" name="clk0" .*dir="input" .*vartype="logic" origName="clk0" clocker="true" public="true"\/\>/i);
file_grep("$out_filename", qr/\<var fl="d75" loc=".*?" name="clk1" .*dir="input" .*vartype="logic" origName="clk1" clocker="true" public="true"\/\>/i);
file_grep("$out_filename", qr/\<var fl="d76" loc=".*?" name="clk2" .*dir="input" .*vartype="logic" origName="clk2" clocker="true" public="true"\/\>/i);
}
execute(

8
test_regress/t/t_clk_concat_vlt.pl
View File

@ -18,10 +18,10 @@ compile(
);
if ($Self->{vlt_all}) {
file_grep("$out_filename", qr/\<var fl="e78" loc=".*?" name="clk0" dtype_id="1" dir="input" vartype="logic" origName="clk0" clocker="true" public="true"\/\>/i);
file_grep("$out_filename", qr/\<var fl="e79" loc=".*?" name="clk1" dtype_id="1" dir="input" vartype="logic" origName="clk1" clocker="true" public="true"\/\>/i);
file_grep("$out_filename", qr/\<var fl="e80" loc=".*?" name="clk2" dtype_id="1" dir="input" vartype="logic" origName="clk2" clocker="true" public="true"\/\>/i);
file_grep("$out_filename", qr/\<var fl="e82" loc=".*?" name="data_in" dtype_id="1" dir="input" vartype="logic" origName="data_in" clocker="false" public="true"\/\>/i);
file_grep("$out_filename", qr/\<var fl="e78" loc=".*?" name="clk0" .*dir="input" .*vartype="logic" origName="clk0" clocker="true" public="true"\/\>/i);
file_grep("$out_filename", qr/\<var fl="e79" loc=".*?" name="clk1" .*dir="input" .*vartype="logic" origName="clk1" clocker="true" public="true"\/\>/i);
file_grep("$out_filename", qr/\<var fl="e80" loc=".*?" name="clk2" .*dir="input" .*vartype="logic" origName="clk2" clocker="true" public="true"\/\>/i);
file_grep("$out_filename", qr/\<var fl="e82" loc=".*?" name="data_in" .*dir="input" .*vartype="logic" origName="data_in" clocker="false" public="true"\/\>/i);
}
execute(

40
test_regress/t/t_var_port_xml.out
View File

@ -57,54 +57,54 @@
</cells>
<netlist>
<module fl="d18" loc="d,18,8,18,11" name="mh2" origName="mh2">
<var fl="d18" loc="d,18,27,18,47" name="x_inout_wire_integer" dtype_id="1" dir="inout" vartype="integer" origName="x_inout_wire_integer"/>
<var fl="d18" loc="d,18,27,18,47" name="x_inout_wire_integer" dtype_id="1" dir="inout" pinIndex="1" vartype="integer" origName="x_inout_wire_integer"/>
</module>
<module fl="d24" loc="d,24,8,24,11" name="mh5" origName="mh5">
<var fl="d24" loc="d,24,19,24,37" name="x_input_wire_logic" dtype_id="2" dir="input" vartype="logic" origName="x_input_wire_logic"/>
<var fl="d24" loc="d,24,19,24,37" name="x_input_wire_logic" dtype_id="2" dir="input" pinIndex="1" vartype="logic" origName="x_input_wire_logic"/>
</module>
<module fl="d26" loc="d,26,8,26,11" name="mh6" origName="mh6">
<var fl="d26" loc="d,26,23,26,40" name="x_input_var_logic" dtype_id="2" dir="input" vartype="logic" origName="x_input_var_logic"/>
<var fl="d26" loc="d,26,23,26,40" name="x_input_var_logic" dtype_id="2" dir="input" pinIndex="1" vartype="logic" origName="x_input_var_logic"/>
</module>
<module fl="d28" loc="d,28,8,28,11" name="mh7" origName="mh7">
<var fl="d28" loc="d,28,31,28,50" name="x_input_var_integer" dtype_id="1" dir="input" vartype="integer" origName="x_input_var_integer"/>
<var fl="d28" loc="d,28,31,28,50" name="x_input_var_integer" dtype_id="1" dir="input" pinIndex="1" vartype="integer" origName="x_input_var_integer"/>
</module>
<module fl="d30" loc="d,30,8,30,11" name="mh8" origName="mh8">
<var fl="d30" loc="d,30,20,30,39" name="x_output_wire_logic" dtype_id="2" dir="output" vartype="logic" origName="x_output_wire_logic"/>
<var fl="d30" loc="d,30,20,30,39" name="x_output_wire_logic" dtype_id="2" dir="output" pinIndex="1" vartype="logic" origName="x_output_wire_logic"/>
</module>
<module fl="d32" loc="d,32,8,32,11" name="mh9" origName="mh9">
<var fl="d32" loc="d,32,24,32,42" name="x_output_var_logic" dtype_id="2" dir="output" vartype="logic" origName="x_output_var_logic"/>
<var fl="d32" loc="d,32,24,32,42" name="x_output_var_logic" dtype_id="2" dir="output" pinIndex="1" vartype="logic" origName="x_output_var_logic"/>
</module>
<module fl="d34" loc="d,34,8,34,12" name="mh10" origName="mh10">
<var fl="d34" loc="d,34,33,34,62" name="x_output_wire_logic_signed_p6" dtype_id="3" dir="output" vartype="logic" origName="x_output_wire_logic_signed_p6"/>
<var fl="d34" loc="d,34,33,34,62" name="x_output_wire_logic_signed_p6" dtype_id="3" dir="output" pinIndex="1" vartype="logic" origName="x_output_wire_logic_signed_p6"/>
</module>
<module fl="d36" loc="d,36,8,36,12" name="mh11" origName="mh11">
<var fl="d36" loc="d,36,28,36,48" name="x_output_var_integer" dtype_id="1" dir="output" vartype="integer" origName="x_output_var_integer"/>
<var fl="d36" loc="d,36,28,36,48" name="x_output_var_integer" dtype_id="1" dir="output" pinIndex="1" vartype="integer" origName="x_output_var_integer"/>
</module>
<module fl="d38" loc="d,38,8,38,12" name="mh12" origName="mh12">
<var fl="d38" loc="d,38,23,38,37" name="x_ref_logic_p6" dtype_id="4" dir="ref" vartype="logic" origName="x_ref_logic_p6"/>
<var fl="d38" loc="d,38,23,38,37" name="x_ref_logic_p6" dtype_id="4" dir="ref" pinIndex="1" vartype="logic" origName="x_ref_logic_p6"/>
</module>
<module fl="d40" loc="d,40,8,40,12" name="mh13" origName="mh13">
<var fl="d40" loc="d,40,17,40,35" name="x_ref_var_logic_u6" dtype_id="5" dir="ref" vartype="port" origName="x_ref_var_logic_u6"/>
<var fl="d40" loc="d,40,17,40,35" name="x_ref_var_logic_u6" dtype_id="5" dir="ref" pinIndex="1" vartype="port" origName="x_ref_var_logic_u6"/>
</module>
<module fl="d50" loc="d,50,8,50,12" name="mh17" origName="mh17">
<var fl="d50" loc="d,50,31,50,50" name="x_input_var_integer" dtype_id="1" dir="input" vartype="integer" origName="x_input_var_integer"/>
<var fl="d50" loc="d,50,57,50,75" name="y_input_wire_logic" dtype_id="2" dir="input" vartype="logic" origName="y_input_wire_logic"/>
<var fl="d50" loc="d,50,31,50,50" name="x_input_var_integer" dtype_id="1" dir="input" pinIndex="1" vartype="integer" origName="x_input_var_integer"/>
<var fl="d50" loc="d,50,57,50,75" name="y_input_wire_logic" dtype_id="2" dir="input" pinIndex="2" vartype="logic" origName="y_input_wire_logic"/>
</module>
<module fl="d52" loc="d,52,8,52,12" name="mh18" origName="mh18">
<var fl="d52" loc="d,52,24,52,42" name="x_output_var_logic" dtype_id="2" dir="output" vartype="logic" origName="x_output_var_logic"/>
<var fl="d52" loc="d,52,50,52,68" name="y_input_wire_logic" dtype_id="2" dir="input" vartype="logic" origName="y_input_wire_logic"/>
<var fl="d52" loc="d,52,24,52,42" name="x_output_var_logic" dtype_id="2" dir="output" pinIndex="1" vartype="logic" origName="x_output_var_logic"/>
<var fl="d52" loc="d,52,50,52,68" name="y_input_wire_logic" dtype_id="2" dir="input" pinIndex="2" vartype="logic" origName="y_input_wire_logic"/>
</module>
<module fl="d54" loc="d,54,8,54,12" name="mh19" origName="mh19">
<var fl="d54" loc="d,54,33,54,62" name="x_output_wire_logic_signed_p6" dtype_id="3" dir="output" vartype="logic" origName="x_output_wire_logic_signed_p6"/>
<var fl="d54" loc="d,54,72,54,92" name="y_output_var_integer" dtype_id="1" dir="output" vartype="integer" origName="y_output_var_integer"/>
<var fl="d54" loc="d,54,33,54,62" name="x_output_wire_logic_signed_p6" dtype_id="3" dir="output" pinIndex="1" vartype="logic" origName="x_output_wire_logic_signed_p6"/>
<var fl="d54" loc="d,54,72,54,92" name="y_output_var_integer" dtype_id="1" dir="output" pinIndex="2" vartype="integer" origName="y_output_var_integer"/>
</module>
<module fl="d56" loc="d,56,8,56,12" name="mh20" origName="mh20">
<var fl="d56" loc="d,56,23,56,41" name="x_ref_var_logic_p6" dtype_id="4" dir="ref" vartype="logic" origName="x_ref_var_logic_p6"/>
<var fl="d56" loc="d,56,43,56,61" name="y_ref_var_logic_p6" dtype_id="4" dir="ref" vartype="logic" origName="y_ref_var_logic_p6"/>
<var fl="d56" loc="d,56,23,56,41" name="x_ref_var_logic_p6" dtype_id="4" dir="ref" pinIndex="1" vartype="logic" origName="x_ref_var_logic_p6"/>
<var fl="d56" loc="d,56,43,56,61" name="y_ref_var_logic_p6" dtype_id="4" dir="ref" pinIndex="2" vartype="logic" origName="y_ref_var_logic_p6"/>
</module>
<module fl="d58" loc="d,58,8,58,12" name="mh21" origName="mh21">
<var fl="d58" loc="d,58,17,58,33" name="ref_var_logic_u6" dtype_id="6" dir="ref" vartype="port" origName="ref_var_logic_u6"/>
<var fl="d58" loc="d,58,41,58,56" name="y_ref_var_logic" dtype_id="2" dir="ref" vartype="logic" origName="y_ref_var_logic"/>
<var fl="d58" loc="d,58,17,58,33" name="ref_var_logic_u6" dtype_id="6" dir="ref" pinIndex="1" vartype="port" origName="ref_var_logic_u6"/>
<var fl="d58" loc="d,58,41,58,56" name="y_ref_var_logic" dtype_id="2" dir="ref" pinIndex="2" vartype="logic" origName="y_ref_var_logic"/>
</module>
<typetable fl="a0" loc="a,0,0,0,0">
<unpackarraydtype fl="d58" loc="d,58,34,58,35" id="6" sub_dtype_id="2">

18
test_regress/t/t_xml_first.out
View File

@ -18,9 +18,9 @@
</cells>
<netlist>
<module fl="d7" loc="d,7,8,7,9" name="t" origName="t" topModule="1">
<var fl="d13" loc="d,13,10,13,13" name="clk" dtype_id="1" dir="input" vartype="logic" origName="clk"/>
<var fl="d14" loc="d,14,16,14,17" name="d" dtype_id="2" dir="input" vartype="logic" origName="d"/>
<var fl="d15" loc="d,15,22,15,23" name="q" dtype_id="2" dir="output" vartype="logic" origName="q"/>
<var fl="d13" loc="d,13,10,13,13" name="clk" dtype_id="1" dir="input" pinIndex="2" vartype="logic" origName="clk"/>
<var fl="d14" loc="d,14,16,14,17" name="d" dtype_id="2" dir="input" pinIndex="3" vartype="logic" origName="d"/>
<var fl="d15" loc="d,15,22,15,23" name="q" dtype_id="2" dir="output" pinIndex="1" vartype="logic" origName="q"/>
<var fl="d17" loc="d,17,22,17,29" name="between" dtype_id="2" vartype="logic" origName="between"/>
<instance fl="d20" loc="d,20,4,20,9" name="cell1" defName="mod1__W4" origName="cell1">
<port fl="d20" loc="d,20,12,20,13" name="q" direction="out" portIndex="1">
@ -49,9 +49,9 @@
<var fl="d32" loc="d,32,15,32,20" name="WIDTH" dtype_id="3" vartype="logic" origName="WIDTH" param="true">
<const fl="d19" loc="d,19,18,19,19" name="32&apos;sh4" dtype_id="3"/>
</var>
<var fl="d34" loc="d,34,24,34,27" name="clk" dtype_id="1" dir="input" vartype="logic" origName="clk"/>
<var fl="d35" loc="d,35,30,35,31" name="d" dtype_id="2" dir="input" vartype="logic" origName="d"/>
<var fl="d36" loc="d,36,30,36,31" name="q" dtype_id="2" dir="output" vartype="logic" origName="q"/>
<var fl="d34" loc="d,34,24,34,27" name="clk" dtype_id="1" dir="input" pinIndex="1" vartype="logic" origName="clk"/>
<var fl="d35" loc="d,35,30,35,31" name="d" dtype_id="2" dir="input" pinIndex="2" vartype="logic" origName="d"/>
<var fl="d36" loc="d,36,30,36,31" name="q" dtype_id="2" dir="output" pinIndex="3" vartype="logic" origName="q"/>
<var fl="d39" loc="d,39,15,39,22" name="IGNORED" dtype_id="3" vartype="logic" origName="IGNORED" localparam="true">
<const fl="d39" loc="d,39,25,39,26" name="32&apos;sh1" dtype_id="3"/>
</var>
@ -68,9 +68,9 @@
</always>
</module>
<module fl="d46" loc="d,46,8,46,12" name="mod2" origName="mod2">
<var fl="d48" loc="d,48,10,48,13" name="clk" dtype_id="1" dir="input" vartype="logic" origName="clk"/>
<var fl="d49" loc="d,49,16,49,17" name="d" dtype_id="2" dir="input" vartype="logic" origName="d"/>
<var fl="d50" loc="d,50,22,50,23" name="q" dtype_id="2" dir="output" vartype="logic" origName="q"/>
<var fl="d48" loc="d,48,10,48,13" name="clk" dtype_id="1" dir="input" pinIndex="1" vartype="logic" origName="clk"/>
<var fl="d49" loc="d,49,16,49,17" name="d" dtype_id="2" dir="input" pinIndex="2" vartype="logic" origName="d"/>
<var fl="d50" loc="d,50,22,50,23" name="q" dtype_id="2" dir="output" pinIndex="3" vartype="logic" origName="q"/>
<contassign fl="d53" loc="d,53,13,53,14" dtype_id="2">
<varref fl="d53" loc="d,53,15,53,16" name="d" dtype_id="2"/>
<varref fl="d53" loc="d,53,11,53,12" name="q" dtype_id="2"/>

6
test_regress/t/t_xml_flat.out
View File

@ -15,9 +15,9 @@
</cells>
<netlist>
<module fl="d7" loc="d,7,8,7,9" name="TOP" origName="TOP" topModule="1" public="true">
<var fl="d13" loc="d,13,10,13,13" name="clk" dtype_id="1" dir="input" vartype="logic" origName="clk" clocker="true" public="true"/>
<var fl="d14" loc="d,14,16,14,17" name="d" dtype_id="2" dir="input" vartype="logic" origName="d" public="true"/>
<var fl="d15" loc="d,15,22,15,23" name="q" dtype_id="2" dir="output" vartype="logic" origName="q" public="true"/>
<var fl="d13" loc="d,13,10,13,13" name="clk" dtype_id="1" dir="input" pinIndex="2" vartype="logic" origName="clk" clocker="true" public="true"/>
<var fl="d14" loc="d,14,16,14,17" name="d" dtype_id="2" dir="input" pinIndex="3" vartype="logic" origName="d" public="true"/>
<var fl="d15" loc="d,15,22,15,23" name="q" dtype_id="2" dir="output" pinIndex="1" vartype="logic" origName="q" public="true"/>
<var fl="d13" loc="d,13,10,13,13" name="t.clk" dtype_id="1" vartype="logic" origName="clk"/>
<var fl="d14" loc="d,14,16,14,17" name="t.d" dtype_id="2" vartype="logic" origName="d"/>
<var fl="d15" loc="d,15,22,15,23" name="t.q" dtype_id="2" vartype="logic" origName="q"/>

2
test_regress/t/t_xml_flat_no_inline_mod.out
View File

@ -15,7 +15,7 @@
</cells>
<netlist>
<module fl="d11" loc="d,11,8,11,11" name="TOP" origName="TOP" topModule="1" public="true">
<var fl="d11" loc="d,11,24,11,29" name="i_clk" dtype_id="1" dir="input" vartype="logic" origName="i_clk" public="true"/>
<var fl="d11" loc="d,11,24,11,29" name="i_clk" dtype_id="1" dir="input" pinIndex="1" vartype="logic" origName="i_clk" public="true"/>
<var fl="d11" loc="d,11,24,11,29" name="top.i_clk" dtype_id="1" vartype="logic" origName="i_clk"/>
<var fl="d7" loc="d,7,24,7,29" name="top.f.i_clk" dtype_id="1" vartype="logic" origName="i_clk"/>
<topscope fl="d11" loc="d,11,8,11,11">

2
test_regress/t/t_xml_flat_pub_mod.out
View File

@ -15,7 +15,7 @@
</cells>
<netlist>
<module fl="d11" loc="d,11,8,11,11" name="TOP" origName="TOP" topModule="1" public="true">
<var fl="d11" loc="d,11,24,11,29" name="i_clk" dtype_id="1" dir="input" vartype="logic" origName="i_clk" public="true"/>
<var fl="d11" loc="d,11,24,11,29" name="i_clk" dtype_id="1" dir="input" pinIndex="1" vartype="logic" origName="i_clk" public="true"/>
<var fl="d11" loc="d,11,24,11,29" name="top.i_clk" dtype_id="1" vartype="logic" origName="i_clk"/>
<var fl="d7" loc="d,7,24,7,29" name="top.f.i_clk" dtype_id="1" vartype="logic" origName="i_clk"/>
<topscope fl="d11" loc="d,11,8,11,11">

8
test_regress/t/t_xml_flat_vlvbound.out
View File

@ -15,10 +15,10 @@
</cells>
<netlist>
<module fl="d7" loc="d,7,8,7,21" name="TOP" origName="TOP" topModule="1" public="true">
<var fl="d9" loc="d,9,25,9,28" name="i_a" dtype_id="1" dir="input" vartype="logic" origName="i_a" public="true"/>
<var fl="d10" loc="d,10,25,10,28" name="i_b" dtype_id="1" dir="input" vartype="logic" origName="i_b" public="true"/>
<var fl="d11" loc="d,11,25,11,28" name="o_a" dtype_id="2" dir="output" vartype="logic" origName="o_a" public="true"/>
<var fl="d12" loc="d,12,25,12,28" name="o_b" dtype_id="2" dir="output" vartype="logic" origName="o_b" public="true"/>
<var fl="d9" loc="d,9,25,9,28" name="i_a" dtype_id="1" dir="input" pinIndex="1" vartype="logic" origName="i_a" public="true"/>
<var fl="d10" loc="d,10,25,10,28" name="i_b" dtype_id="1" dir="input" pinIndex="2" vartype="logic" origName="i_b" public="true"/>
<var fl="d11" loc="d,11,25,11,28" name="o_a" dtype_id="2" dir="output" pinIndex="3" vartype="logic" origName="o_a" public="true"/>
<var fl="d12" loc="d,12,25,12,28" name="o_b" dtype_id="2" dir="output" pinIndex="4" vartype="logic" origName="o_b" public="true"/>
<var fl="d9" loc="d,9,25,9,28" name="vlvbound_test.i_a" dtype_id="1" vartype="logic" origName="i_a"/>
<var fl="d10" loc="d,10,25,10,28" name="vlvbound_test.i_b" dtype_id="1" vartype="logic" origName="i_b"/>
<var fl="d11" loc="d,11,25,11,28" name="vlvbound_test.o_a" dtype_id="2" vartype="logic" origName="o_a"/>

2
test_regress/t/t_xml_output.out
View File

@ -15,7 +15,7 @@
</cells>
<netlist>
<module fl="d7" loc="d,7,8,7,9" name="m" origName="m">
<var fl="d8" loc="d,8,10,8,13" name="clk" tag="foo_op" dtype_id="1" dir="input" vartype="logic" origName="clk"/>
<var fl="d8" loc="d,8,10,8,13" name="clk" tag="foo_op" dtype_id="1" dir="input" pinIndex="1" vartype="logic" origName="clk"/>
</module>
<typetable fl="a0" loc="a,0,0,0,0">
<basicdtype fl="d8" loc="d,8,10,8,13" id="1" name="logic"/>

6
test_regress/t/t_xml_tag.out
View File

@ -17,9 +17,9 @@
</cells>
<netlist>
<module fl="d12" loc="d,12,8,12,9" name="m" origName="m" topModule="1">
<var fl="d14" loc="d,14,11,14,17" name="clk_ip" tag="clk_ip" dtype_id="1" dir="input" vartype="logic" origName="clk_ip"/>
<var fl="d15" loc="d,15,11,15,17" name="rst_ip" dtype_id="1" dir="input" vartype="logic" origName="rst_ip"/>
<var fl="d16" loc="d,16,11,16,17" name="foo_op" tag="foo_op" dtype_id="1" dir="output" vartype="logic" origName="foo_op"/>
<var fl="d14" loc="d,14,11,14,17" name="clk_ip" tag="clk_ip" dtype_id="1" dir="input" pinIndex="1" vartype="logic" origName="clk_ip"/>
<var fl="d15" loc="d,15,11,15,17" name="rst_ip" dtype_id="1" dir="input" pinIndex="2" vartype="logic" origName="rst_ip"/>
<var fl="d16" loc="d,16,11,16,17" name="foo_op" tag="foo_op" dtype_id="1" dir="output" pinIndex="3" vartype="logic" origName="foo_op"/>
<typedef fl="d25" loc="d,25,6,25,15" name="my_struct" tag="my_struct" dtype_id="2"/>
<instance fl="d29" loc="d,29,8,29,12" name="itop" defName="ifc" origName="itop"/>
<var fl="d29" loc="d,29,8,29,12" name="itop__Viftop" dtype_id="3" vartype="ifaceref" origName="itop__Viftop"/>