Mario1159/verilator
1
0
Fork 0
forked from github/verilator
Code Pull Requests Releases 1 Activity

Fix real parameters causing bad module names, bug992.

Browse Source
This commit is contained in:
Wilson Snyder 2015-11-04 22:01:21 -05:00
parent 3df23a148a
commit bf5dee955d
4 changed files with 52 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
Changes
View File

@ -5,6 +5,8 @@ indicates the contributor was also the author of the fix; Thanks!
* Verilator 3.879 devel
**** Fix real parameters causing bad module names, bug992. [Johan Bjork]
* Verilator 3.878 2015-11-01

8
src/V3Param.cpp
View File

@ -148,7 +148,7 @@ private:
// Given a compilcated object create a number to use for param module assignment
// Ideally would be relatively stable if design changes (not use pointer value),
// and must return same value given same input node
// Return must presently be numberic so doesn't collide with 'small' alphanumeric parameter names
// Return must presently be numeric so doesn't collide with 'small' alphanumeric parameter names
ValueMap::iterator it = m_valueMap.find(nodep);
if (it != m_valueMap.end()) {
return cvtToStr(it->second);
@ -470,9 +470,13 @@ void ParamVisitor::visitCell(AstCell* nodep) {
// Setting parameter to its default value. Just ignore it.
// This prevents making additional modules, and makes coverage more
// obvious as it won't show up under a unique module page name.
} else {
} else if (!constp->num().isDouble() && !constp->num().isString()
&& !constp->num().isFourState() && !constp->num().isNegative()) {
longname += "_" + paramSmallName(nodep->modp(),pinp->modVarp())+constp->num().ascii(false);
any_overrides = true;
} else {
longname += "_" + paramSmallName(nodep->modp(),pinp->modVarp())+paramValueNumber(constp);
any_overrides = true;
}
}
}

18
test_regress/t/t_param_real.pl Executable file
View File

@ -0,0 +1,18 @@
#!/usr/bin/perl
if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2003 by Wilson Snyder. This program is free software; you can
# redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
compile (
);
execute (
check_finished=>1,
);
ok(1);
1;

26
test_regress/t/t_param_real.v Normal file
View File

@ -0,0 +1,26 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2015 by Johan Bjork
module mod #(
parameter real HZ = 0
);
//verilator no_inline_module
initial begin
if ((HZ-$floor(HZ)) - 0.45 > 0.01) $stop;
if ((HZ-$floor(HZ)) - 0.45 < -0.01) $stop;
end
endmodule
module t();
mod #(.HZ(123.45)) mod1();
mod #(.HZ(24.45)) mod2();
initial begin
if (mod1.HZ != 123.45) $stop;
if (mod2.HZ != 24.45) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
endmodule