diff --git a/docs/CONTRIBUTORS b/docs/CONTRIBUTORS
index 7a800bab7..7a5f72934 100644
--- a/docs/CONTRIBUTORS
+++ b/docs/CONTRIBUTORS
@@ -130,5 +130,6 @@ Yoda Lee
 Yossi Nivin
 Yuri Victorovich
 Yutetsu TAKATSUKASA
+Yu-Sheng Lin
 Yves Mathieu
 Zhanglei Wang
diff --git a/src/V3EmitCModel.cpp b/src/V3EmitCModel.cpp
index 2c2239306..2daf8c4cf 100644
--- a/src/V3EmitCModel.cpp
+++ b/src/V3EmitCModel.cpp
@@ -552,6 +552,11 @@ class EmitCModel final : public EmitCFunc {
                     "elaboration.\");\n");
             puts(/**/ "}");
         }
+        puts(/**/ "if (tfp->isOpen()) {\n");
+        puts(/****/ "vl_fatal(__FILE__, __LINE__, __FILE__,\"'" + topClassName()
+             + +"::trace()' shall not be called after '" + v3Global.opt.traceClassBase()
+             + "C::open()'.\");\n");
+        puts(/**/ "}\n");
         puts(/**/ "if (false && levels && options) {}  // Prevent unused\n");
         puts(/**/ "tfp->spTrace()->addModel(this);\n");
         puts(/**/ "tfp->spTrace()->addInitCb(&" + protect("trace_init") + ", &(vlSymsp->TOP));\n");
diff --git a/test_regress/t/t_trace_open_wrong_order.cpp b/test_regress/t/t_trace_open_wrong_order.cpp
new file mode 100644
index 000000000..4faa6dd5b
--- /dev/null
+++ b/test_regress/t/t_trace_open_wrong_order.cpp
@@ -0,0 +1,25 @@
+// -*- mode: C++; c-file-style: "cc-mode" -*-
+//
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2010 by Yu-Sheng Lin.
+// SPDX-License-Identifier: CC0-1.0
+
+#include <verilated.h>
+#include <verilated_vcd_c.h>
+
+#include "Vt_trace_open_wrong_order.h"
+using namespace std;
+
+int main(int argc, char** argv) {
+    VerilatedContext ctx;
+    VerilatedVcdC tfp;
+    Vt_trace_open_wrong_order dut;
+    ctx.traceEverOn(true);
+    tfp.open("dump.vcd");  // Error! shall put to the next line!
+    dut.trace(&tfp, 99);  // Error!
+    tfp.dump(0);
+    tfp.close();
+    return 0;
+}
diff --git a/test_regress/t/t_trace_open_wrong_order.pl b/test_regress/t/t_trace_open_wrong_order.pl
new file mode 100755
index 000000000..a7c8b6c51
--- /dev/null
+++ b/test_regress/t/t_trace_open_wrong_order.pl
@@ -0,0 +1,30 @@
+#!/usr/bin/env perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2022 by Yu-Sheng Lin. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+scenarios(simulator => 1);
+
+if ($Self->{vlt_all}) {
+    compile(
+        verilator_flags2 => ["--cc --trace --exe $Self->{t_dir}/$Self->{name}.cpp"],
+        make_top_shell => 0,
+        make_main => 0,
+        );
+} else {
+    compile(
+        );
+}
+
+execute(
+    fails => 1
+    );
+file_grep($Self->{run_log_filename}, qr/::trace\(\)' shall not be called after 'VerilatedVcdC::open\(\)'/i);
+
+ok(1);
+1;
diff --git a/test_regress/t/t_trace_open_wrong_order.v b/test_regress/t/t_trace_open_wrong_order.v
new file mode 100644
index 000000000..60a7504fd
--- /dev/null
+++ b/test_regress/t/t_trace_open_wrong_order.v
@@ -0,0 +1,8 @@
+// DESCRIPTION: Verilator: Verilog dummy test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2022 by Yu-Sheng Lin.
+// SPDX-License-Identifier: CC0-1.0
+
+module t(input clk);
+endmodule