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Fix clocker attributes to not propagate on concats.

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This commit is contained in:
Wilson Snyder 2018-06-22 19:46:27 -04:00
parent 86d85412e1
commit b8842f7e55
6 changed files with 265 additions and 11 deletions
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@ -16,6 +16,8 @@ The contributors that suggested a given feature are shown in []. Thanks!
**** Fix Verilation performance issues, bug1316. [John Coiner]
**** Fix clocker attributes to not propagate on concats. [John Coiner]
* Verilator 3.925 devel

16
src/V3Order.cpp
View File

@ -379,27 +379,26 @@ public:
class OrderClkAssVisitor : public AstNVisitor {
private:
bool m_clkAss; // There is signals marked as clocker in the assignment
// METHODS
VL_DEBUG_FUNC; // Declare debug()
virtual void visit(AstNodeAssign* nodep) {
if (const AstVarRef* varrefp = VN_CAST(nodep->lhsp(), VarRef) )
if (const AstVarRef* varrefp = VN_CAST(nodep->lhsp(), VarRef)) {
if (varrefp->varp()->attrClocker() == AstVarAttrClocker::CLOCKER_YES) {
m_clkAss = true;
UINFO(6, "node was marked as clocker "<<varrefp<<endl);
}
}
iterateChildren(nodep->rhsp());
}
virtual void visit(AstVarRef* nodep) {
if (nodep->varp()->attrClocker() == AstVarAttrClocker::CLOCKER_YES) {
m_clkAss = true;
UINFO(6, "node was marked as clocker "<<nodep<<endl);
}
// Previous versions checked attrClocker() here, but this breaks
// the updated t_clocker VCD test.
// If reenable this visitor note AstNodeMath short circuit below
}
virtual void visit(AstNodeMath* nodep) {} // Accelerate
virtual void visit(AstNode* nodep) {
iterateChildren(nodep);
}
public:
// CONSTUCTORS
explicit OrderClkAssVisitor(AstNode* nodep) {
@ -407,9 +406,8 @@ public:
iterate(nodep);
}
virtual ~OrderClkAssVisitor() {}
// METHODS
bool isClkAss() {return m_clkAss;}
bool isClkAss() { return m_clkAss; }
};

174
test_regress/t/t_clocker.out Normal file
View File

@ -0,0 +1,174 @@
$version Generated by VerilatedVcd $end
$date Fri Jun 22 19:23:24 2018
$end
$timescale 1ns $end
$scope module top $end
$var wire 1 $ clk $end
$var wire 1 % res $end
$var wire 16 ' res16 [15:0] $end
$var wire 8 & res8 [7:0] $end
$scope module $unit $end
$var wire 32 + ID_MSB [31:0] $end
$upscope $end
$scope module t $end
$var wire 1 $ clk $end
$var wire 8 ( clkSet [7:0] $end
$var wire 1 $ clk_1 $end
$var wire 3 ) clk_3 [2:0] $end
$var wire 4 * clk_4 [3:0] $end
$var wire 1 $ clk_final $end
$var wire 8 # count [7:0] $end
$var wire 1 % res $end
$var wire 16 ' res16 [15:0] $end
$var wire 8 & res8 [7:0] $end
$upscope $end
$upscope $end
$enddefinitions $end
#0
b00000000 #
0$
0%
b00000000 &
b0000000000000000 '
b00000000 (
b000 )
b0000 *
b00000000000000000000000000000001 +
#10
b00000001 #
1$
1%
b11101111 &
b0000000111111111 '
b11111111 (
b111 )
b1111 *
#15
b00000010 #
0$
0%
b00000000 &
b0000001000000000 '
b00000000 (
b000 )
b0000 *
#20
b00000011 #
1$
1%
b11101111 &
b0000001111111111 '
b11111111 (
b111 )
b1111 *
#25
b00000100 #
0$
0%
b00000000 &
b0000010000000000 '
b00000000 (
b000 )
b0000 *
#30
b00000101 #
1$
1%
b11101111 &
b0000010111111111 '
b11111111 (
b111 )
b1111 *
#35
b00000110 #
0$
0%
b00000000 &
b0000011000000000 '
b00000000 (
b000 )
b0000 *
#40
b00000111 #
1$
1%
b11101111 &
b0000011111111111 '
b11111111 (
b111 )
b1111 *
#45
b00001000 #
0$
0%
b00000000 &
b0000100000000000 '
b00000000 (
b000 )
b0000 *
#50
b00001001 #
1$
1%
b11101111 &
b0000100111111111 '
b11111111 (
b111 )
b1111 *
#55
b00001010 #
0$
0%
b00000000 &
b0000101000000000 '
b00000000 (
b000 )
b0000 *
#60
b00001011 #
1$
1%
b11101111 &
b0000101111111111 '
b11111111 (
b111 )
b1111 *
#65
b00001100 #
0$
0%
b00000000 &
b0000110000000000 '
b00000000 (
b000 )
b0000 *
#70
b00001101 #
1$
1%
b11101111 &
b0000110111111111 '
b11111111 (
b111 )
b1111 *
#75
b00001110 #
0$
0%
b00000000 &
b0000111000000000 '
b00000000 (
b000 )
b0000 *
#80
b00001111 #
1$
1%
b11101111 &
b0000111111111111 '
b11111111 (
b111 )
b1111 *

4
test_regress/t/t_clocker.pl
View File

@ -10,12 +10,14 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); di
scenarios(simulator => 1);
compile(
# verilator_flags2 => ["-Wno-UNOPTFLAT"]
verilator_flags2 => ["--trace"]
);
execute(
check_finished => 1,
);
vcd_identical("$Self->{obj_dir}/simx.vcd", "t/$Self->{name}.out");
ok(1);
1;

76
test_regress/t/t_order_clkinst.out Normal file
View File

@ -0,0 +1,76 @@
$version Generated by VerilatedVcd $end
$date Fri Jun 22 19:27:45 2018
$end
$timescale 1ns $end
$scope module top $end
$var wire 1 / clk $end
$scope module t $end
$var wire 32 % c1_count [31:0] $end
$var wire 1 # c1_start $end
$var wire 32 ( c3_count [31:0] $end
$var wire 1 ' c3_start $end
$var wire 1 / clk $end
$var wire 8 $ cyc [7:0] $end
$var wire 32 & s2_count [31:0] $end
$var wire 1 # s2_start $end
$scope module c1 $end
$var wire 32 % count [31:0] $end
$var wire 32 * runner [31:0] $end
$var wire 32 ) runnerm1 [31:0] $end
$var wire 1 # start $end
$upscope $end
$scope module c3 $end
$var wire 32 ( count [31:0] $end
$var wire 32 . runner [31:0] $end
$var wire 32 - runnerm1 [31:0] $end
$var wire 1 ' start $end
$upscope $end
$scope module s2 $end
$var wire 32 & count [31:0] $end
$var wire 32 , runner [31:0] $end
$var wire 32 + runnerm1 [31:0] $end
$var wire 1 # start $end
$upscope $end
$upscope $end
$upscope $end
$enddefinitions $end
#0
0#
b00000000 $
b00000000000000000000000000000000 %
b00000000000000000000000000000000 &
0'
b00000000000000000000000000000000 (
b11111111111111111111111111111111 )
b00000000000000000000000000000000 *
b11111111111111111111111111111111 +
b00000000000000000000000000000000 ,
b11111111111111111111111111111111 -
b00000000000000000000000000000000 .
0/
#10
b00000001 $
1/
#15
0/
#20
1#
b00000010 $
b00000000000000000000000000000011 %
b00000000000000000000000000000011 &
1'
b00000000000000000000000000000101 (
1/
#25
0/
#30
b00000011 $
1/
#35
0/
#40
b00000100 $
1/

4
test_regress/t/t_order_clkinst.pl
View File

@ -15,9 +15,11 @@ scenarios(simulator => 1);
# closely enough to pass the same test?
# If not -- probably we should switch this to be vlt-only.
compile();
compile(verilator_flags2 => ["--trace"]);
execute(check_finished => 1);
vcd_identical("$Self->{obj_dir}/simx.vcd", "t/$Self->{name}.out");
ok(1);
1;