forked from github/verilator
Fix generate unrolling with function call, bug830.
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@ -5,6 +5,8 @@ indicates the contributor was also the author of the fix; Thanks!
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* Verilator 3.865 devel
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**** Fix generate unrolling with function call, bug830. [Steven Slatter]
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* Verilator 3.864 2014-09-21
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@ -164,15 +164,27 @@ private:
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bool gt = condp->castGt() || condp->castGtS();
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bool gte = condp->castGte() || condp->castGteS();
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if (!lt && !lte && !gt && !gte)
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return cantUnroll(nodep, "condition not <= or <");
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AstNodeBiop* condBip = condp->castNodeBiop();
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if (!condBip->rhsp()->castVarRef())
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return cantUnroll(nodep, "condition not <=, <, >= or >");
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AstNodeBiop* cmpInstrp = condp->castNodeBiop();
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bool cmpVarLhs;
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if (cmpInstrp->lhsp()->castVarRef()
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&& cmpInstrp->lhsp()->castVarRef()->varp() == m_forVarp
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&& cmpInstrp->lhsp()->castVarRef()->varScopep() == m_forVscp) {
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cmpVarLhs = true;
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} else if (cmpInstrp->rhsp()->castVarRef()
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&& cmpInstrp->rhsp()->castVarRef()->varp() == m_forVarp
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&& cmpInstrp->rhsp()->castVarRef()->varScopep() == m_forVscp) {
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cmpVarLhs = false;
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} else if (!cmpInstrp->rhsp()->castVarRef()) {
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return cantUnroll(nodep, "no variable on rhs of condition");
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if (condBip->rhsp()->castVarRef()->varp() != m_forVarp
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|| condBip->rhsp()->castVarRef()->varScopep() != m_forVscp)
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} else {
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return cantUnroll(nodep, "different variable in condition");
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if (m_generate) V3Const::constifyParamsEdit(condBip->lhsp()); // rhsp may change
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AstConst* constStopp = condBip->lhsp()->castConst();
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}
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if (m_generate) V3Const::constifyParamsEdit(cmpVarLhs ? cmpInstrp->rhsp()
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: cmpInstrp->lhsp()); // rhsp/lhsp may change
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AstConst* constStopp = (cmpVarLhs ? cmpInstrp->rhsp()->castConst()
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: cmpInstrp->lhsp()->castConst());
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if (!constStopp) return cantUnroll(nodep, "non-constant final value");
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UINFO(8, " Stop expr ok: "<<constStopp<<endl);
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//
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@ -217,9 +229,9 @@ private:
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if (m_varAssignHit) return cantUnroll(nodep, "genvar assigned *inside* loop");
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//
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// Finally, we can do it
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forUnroller(nodep, initp, precondsp, condp, incp, bodysp,
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forUnroller(nodep, initp, precondsp, incp, bodysp,
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constInitp->num(),
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condBip, constStopp->num(),
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cmpInstrp, constStopp->num(), cmpVarLhs,
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incInstrp, constIncp->num()); nodep = NULL;
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// Cleanup
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return true;
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@ -227,10 +239,10 @@ private:
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void forUnroller(AstNode* nodep,
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AstNode* initp,
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AstNode* precondsp, AstNode* condp,
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AstNode* precondsp,
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AstNode* incp, AstNode* bodysp,
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const V3Number& numInit,
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AstNodeBiop* cmpInstrp, const V3Number& numStop,
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AstNodeBiop* cmpInstrp, const V3Number& numStop, bool cmpVarLhs,
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AstNodeBiop* incInstrp, const V3Number& numInc) {
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UINFO(4, " Unroll for var="<<numInit<<"; var<"<<numStop<<"; var+="<<numInc<<endl);
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UINFO(6, " cmpI "<<cmpInstrp<<endl);
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@ -270,7 +282,11 @@ private:
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UINFO(8," Looping "<<loopValue<<endl);
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// if loopValue<valStop
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V3Number contin (nodep->fileline(), 1);
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cmpInstrp->numberOperate(contin, numStop, loopValue);
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if (cmpVarLhs) {
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cmpInstrp->numberOperate(contin, loopValue, numStop);
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} else {
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cmpInstrp->numberOperate(contin, numStop, loopValue);
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}
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if (contin.isEqZero()) {
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break; // Done with the loop
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} else {
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18
test_regress/t/t_unroll_genf.pl
Executable file
18
test_regress/t/t_unroll_genf.pl
Executable file
@ -0,0 +1,18 @@
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#!/usr/bin/perl
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if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
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# DESCRIPTION: Verilator: Verilog Test driver/expect definition
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#
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# Copyright 2003 by Wilson Snyder. This program is free software; you can
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# redistribute it and/or modify it under the terms of either the GNU
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# Lesser General Public License Version 3 or the Perl Artistic License
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# Version 2.0.
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compile (
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);
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execute (
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check_finished=>1,
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);
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ok(1);
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1;
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29
test_regress/t/t_unroll_genf.v
Normal file
29
test_regress/t/t_unroll_genf.v
Normal file
@ -0,0 +1,29 @@
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2004 by Wilson Snyder.
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//bug830
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module sub();
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endmodule
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function integer cdiv(input integer x);
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begin
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cdiv = 10;
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end
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endfunction
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module t (/*AUTOARG*/);
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genvar j;
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generate
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for (j = 0; j < cdiv(10); j=j+1)
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sub sub();
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endgenerate
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initial begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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