Fix generate unrolling with function call, bug830.

This commit is contained in:
Wilson Snyder 2014-10-15 21:29:37 -04:00
parent 6ba90e3a50
commit b73edc0564
4 changed files with 77 additions and 12 deletions

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@ -5,6 +5,8 @@ indicates the contributor was also the author of the fix; Thanks!
* Verilator 3.865 devel
**** Fix generate unrolling with function call, bug830. [Steven Slatter]
* Verilator 3.864 2014-09-21

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@ -164,15 +164,27 @@ private:
bool gt = condp->castGt() || condp->castGtS();
bool gte = condp->castGte() || condp->castGteS();
if (!lt && !lte && !gt && !gte)
return cantUnroll(nodep, "condition not <= or <");
AstNodeBiop* condBip = condp->castNodeBiop();
if (!condBip->rhsp()->castVarRef())
return cantUnroll(nodep, "condition not <=, <, >= or >");
AstNodeBiop* cmpInstrp = condp->castNodeBiop();
bool cmpVarLhs;
if (cmpInstrp->lhsp()->castVarRef()
&& cmpInstrp->lhsp()->castVarRef()->varp() == m_forVarp
&& cmpInstrp->lhsp()->castVarRef()->varScopep() == m_forVscp) {
cmpVarLhs = true;
} else if (cmpInstrp->rhsp()->castVarRef()
&& cmpInstrp->rhsp()->castVarRef()->varp() == m_forVarp
&& cmpInstrp->rhsp()->castVarRef()->varScopep() == m_forVscp) {
cmpVarLhs = false;
} else if (!cmpInstrp->rhsp()->castVarRef()) {
return cantUnroll(nodep, "no variable on rhs of condition");
if (condBip->rhsp()->castVarRef()->varp() != m_forVarp
|| condBip->rhsp()->castVarRef()->varScopep() != m_forVscp)
} else {
return cantUnroll(nodep, "different variable in condition");
if (m_generate) V3Const::constifyParamsEdit(condBip->lhsp()); // rhsp may change
AstConst* constStopp = condBip->lhsp()->castConst();
}
if (m_generate) V3Const::constifyParamsEdit(cmpVarLhs ? cmpInstrp->rhsp()
: cmpInstrp->lhsp()); // rhsp/lhsp may change
AstConst* constStopp = (cmpVarLhs ? cmpInstrp->rhsp()->castConst()
: cmpInstrp->lhsp()->castConst());
if (!constStopp) return cantUnroll(nodep, "non-constant final value");
UINFO(8, " Stop expr ok: "<<constStopp<<endl);
//
@ -217,9 +229,9 @@ private:
if (m_varAssignHit) return cantUnroll(nodep, "genvar assigned *inside* loop");
//
// Finally, we can do it
forUnroller(nodep, initp, precondsp, condp, incp, bodysp,
forUnroller(nodep, initp, precondsp, incp, bodysp,
constInitp->num(),
condBip, constStopp->num(),
cmpInstrp, constStopp->num(), cmpVarLhs,
incInstrp, constIncp->num()); nodep = NULL;
// Cleanup
return true;
@ -227,10 +239,10 @@ private:
void forUnroller(AstNode* nodep,
AstNode* initp,
AstNode* precondsp, AstNode* condp,
AstNode* precondsp,
AstNode* incp, AstNode* bodysp,
const V3Number& numInit,
AstNodeBiop* cmpInstrp, const V3Number& numStop,
AstNodeBiop* cmpInstrp, const V3Number& numStop, bool cmpVarLhs,
AstNodeBiop* incInstrp, const V3Number& numInc) {
UINFO(4, " Unroll for var="<<numInit<<"; var<"<<numStop<<"; var+="<<numInc<<endl);
UINFO(6, " cmpI "<<cmpInstrp<<endl);
@ -270,7 +282,11 @@ private:
UINFO(8," Looping "<<loopValue<<endl);
// if loopValue<valStop
V3Number contin (nodep->fileline(), 1);
cmpInstrp->numberOperate(contin, numStop, loopValue);
if (cmpVarLhs) {
cmpInstrp->numberOperate(contin, loopValue, numStop);
} else {
cmpInstrp->numberOperate(contin, numStop, loopValue);
}
if (contin.isEqZero()) {
break; // Done with the loop
} else {

18
test_regress/t/t_unroll_genf.pl Executable file
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@ -0,0 +1,18 @@
#!/usr/bin/perl
if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2003 by Wilson Snyder. This program is free software; you can
# redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
compile (
);
execute (
check_finished=>1,
);
ok(1);
1;

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@ -0,0 +1,29 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2004 by Wilson Snyder.
//bug830
module sub();
endmodule
function integer cdiv(input integer x);
begin
cdiv = 10;
end
endfunction
module t (/*AUTOARG*/);
genvar j;
generate
for (j = 0; j < cdiv(10); j=j+1)
sub sub();
endgenerate
initial begin
$write("*-* All Finished *-*\n");
$finish;
end
endmodule