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Fix wire declarations with size and not range, bug466.

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Wilson Snyder 2013-12-14 19:50:55 -05:00
parent 801b718953
commit b5f5b1fdf9
3 changed files with 4 additions and 1 deletions
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@ -13,6 +13,8 @@ indicates the contributor was also the author of the fix; Thanks!
**** Fix some delayed assignments of typedefed unpacked arrays.
**** Fix wire declarations with size and not range, bug466. [Alex Solomatnikov]
**** Fix parameter pin vs. normal pin error, bug704. [Alex Solomatnikov]

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src/verilog.y
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@ -1879,7 +1879,7 @@ netSigList<varp>: // IEEE: list_of_port_identifiers
netSig<varp>: // IEEE: net_decl_assignment - one element from list_of_port_identifiers
netId sigAttrListE { $$ = VARDONEA($<fl>1,*$1, NULL, $2); }
| netId sigAttrListE '=' expr { $$ = VARDONEA($<fl>1,*$1, NULL, $2); $$->addNext(new AstAssignW($3,new AstVarRef($3,$$->name(),true),$4)); }
| netId rangeList sigAttrListE { $$ = VARDONEA($<fl>1,*$1, $2, $3); }
| netId variable_dimensionList sigAttrListE { $$ = VARDONEA($<fl>1,*$1, $2, $3); }
;
netId<strp>:

1
test_regress/t/t_mem_multiwire.v
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@ -12,6 +12,7 @@ module t (/*AUTOARG*/
// verilator lint_off LITENDIAN
wire [7:0] array [2:0][1:3];
wire [7:0] arrayNoColon [2][3];
// verilator lint_on LITENDIAN
integer cyc; initial cyc=0;