forked from github/verilator
Internals: Fix uninitialized m_alhs
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@ -84,8 +84,10 @@ void AstVar::combineType(AstVarType type) {
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// These flags get combined with the existing settings of the flags.
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if (type==AstVarType::INPUT || type==AstVarType::INOUT)
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m_input = true;
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if (type==AstVarType::OUTPUT || type==AstVarType::INOUT)
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if (type==AstVarType::OUTPUT || type==AstVarType::INOUT) {
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m_output = true;
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m_declOutput = true;
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}
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if (type==AstVarType::INOUT || type==AstVarType::TRIWIRE
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|| type==AstVarType::TRI0 || type==AstVarType::TRI1)
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m_tristate = true;
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@ -709,6 +709,7 @@ private:
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bool m_input:1; // Input or inout
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bool m_output:1; // Output or inout
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bool m_tristate:1; // Inout or triwire or trireg
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bool m_declOutput:1; // Inout or output before tristate resolution
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bool m_primaryIO:1; // In/out to top level (or directly assigned from same)
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bool m_sc:1; // SystemC variable
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bool m_scClocked:1; // SystemC sc_clk<> needed
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@ -734,7 +735,7 @@ private:
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bool m_trace:1; // Trace this variable
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void init() {
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m_input=false; m_output=false; m_tristate=false;
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m_input=false; m_output=false; m_tristate=false; m_declOutput=false;
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m_primaryIO=false;
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m_sc=false; m_scClocked=false; m_scSensitive=false;
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m_usedClock=false; m_usedParam=false; m_usedLoopIdx=false;
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@ -840,6 +841,7 @@ public:
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bool isOutOnly() const { return m_output && !m_input; }
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bool isInout() const { return m_input && m_output; }
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bool isTristate() const { return m_tristate; }
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bool isDeclOutput() const { return m_declOutput; }
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bool isPrimaryIO() const { return m_primaryIO; }
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bool isPrimaryIn() const { return isPrimaryIO() && isInput(); }
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bool isIO() const { return (m_input||m_output); }
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@ -858,9 +858,10 @@ class TristateVisitor : public TristateBaseVisitor {
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public:
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// CONSTUCTORS
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TristateVisitor(AstNode* nodep) {
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m_unique = 0;
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m_cellp = NULL;
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m_modp = NULL;
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m_cellp = NULL;
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m_unique = 0;
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m_alhs = false;
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nodep->accept(*this);
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}
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virtual ~TristateVisitor() {
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