Fix tracing example file output, bug1268.

Changes

@@ -4,6 +4,8 @@ The contributors that suggested a given feature are shown in []. Thanks!
 
 * Verilator 3.919 devel
 
+****  Fix tracing example file output, bug1268. [Enzo Chi]
+
 ****  Fix gate optimization out of memory, add --gate-stmts, bug1260. [Alex Solomatnikov]
 
 ****  Fix compile error on public real parameters by suppressing, bug1261. [Alex Solomatnikov]

examples/tracing_c/sim_main.cpp

@@ -90,6 +90,11 @@ int main(int argc, char** argv, char** env) {
         // Evaluate model
         top->eval();
 
+#if VM_TRACE
+        // Dump trace data for this cycle
+        if (tfp) tfp->dump (main_time);
+#endif
+
         // Read outputs
         VL_PRINTF ("[%" VL_PRI64 "d] clk=%x rstl=%x iquad=%" VL_PRI64 "x"
                    " -> oquad=%" VL_PRI64"x owide=%x_%08x_%08x\n",
@@ -102,7 +107,7 @@ int main(int argc, char** argv, char** env) {
 
     // Close trace if opened
 #if VM_TRACE
-    if (tfp) { tfp->close(); }
+    if (tfp) { tfp->close(); tfp = NULL; }
 #endif
 
     //  Coverage analysis (since test passed)

examples/tracing_sc/sc_main.cpp

@@ -94,10 +94,10 @@ int sc_main(int argc, char* argv[]) {
     const char* flag = Verilated::commandArgsPlusMatch("trace");
     if (flag && 0==strcmp(flag, "+trace")) {
         cout << "Enabling waves into logs/vlt_dump.vcd...\n";
-        VerilatedVcdSc* tfp = new VerilatedVcdSc;
-        top->trace (tfp, 99);
+        tfp = new VerilatedVcdSc;
+        top->trace(tfp, 99);
         mkdir("logs", 0777);
-        tfp->open ("logs/vlt_dump.vcd");
+        tfp->open("logs/vlt_dump.vcd");
     }
 #endif
 
@@ -107,13 +107,15 @@ int sc_main(int argc, char* argv[]) {
         // Flush the wave files each cycle so we can immediately see the output
         // Don't do this in "real" programs, do it in an abort() handler instead
         if (tfp) tfp->flush();
+#endif
+
         // Apply inputs
         if (VL_TIME_Q() > 1 && VL_TIME_Q() < 10) {
             reset_l = !1;       // Assert reset
         } else if (VL_TIME_Q() > 1) {
             reset_l = !0;       // Deassert reset
         }
-#endif
+
         // Simulate 1ns
 #if (SYSTEMC_VERSION>=20070314)
         sc_start(1,SC_NS);
@@ -122,20 +124,23 @@ int sc_main(int argc, char* argv[]) {
 #endif
     }
 
-    //  Close Waves
-#if VM_TRACE
-    if (tfp) tfp->close();
-#endif
-
     // Final model cleanup
     top->final();
 
+    // Close trace if opened
+#if VM_TRACE
+    if (tfp) { tfp->close(); tfp = NULL; }
+#endif
+
     //  Coverage analysis (since test passed)
 #if VM_COVERAGE
     mkdir("logs", 0777);
     VerilatedCov::write("logs/coverage.dat");
 #endif
 
+    // Destroy model
+    delete top; top = NULL;
+
     // Fin
     return 0;
 }

test_regress/driver.pl

@@ -1071,7 +1071,8 @@ sub _make_main {
     print $fh "// General headers\n";
     print $fh "#include \"verilated.h\"\n";
     print $fh "#include \"systemc.h\"\n" if $self->sc;
-    print $fh "#include \"verilated_vcd_c.h\"\n" if $self->{trace};
+    print $fh "#include \"verilated_vcd_c.h\"\n" if $self->{trace} && !$self->sc;
+    print $fh "#include \"verilated_vcd_sc.h\"\n" if $self->{trace} && $self->sc;
     print $fh "#include \"verilated_save.h\"\n" if $self->{savable};
 
     print $fh "$VM_PREFIX * topp;\n";
@@ -1132,7 +1133,8 @@ sub _make_main {
 	$fh->print("\n");
 	$fh->print("#if VM_TRACE\n");
 	$fh->print("    Verilated::traceEverOn(true);\n");
-	$fh->print("    VerilatedVcdC* tfp = new VerilatedVcdC;\n");
+        $fh->print("    VerilatedVcdC* tfp = new VerilatedVcdC;\n") if !$self->sc;
+        $fh->print("    VerilatedVcdSc* tfp = new VerilatedVcdSc;\n") if $self->sc;
 	$fh->print("    topp->trace (tfp, 99);\n");
 	$fh->print("    tfp->open (\"$self->{obj_dir}/simx.vcd\");\n");
 	if ($self->{trace} && !$self->sc) {

test_regress/t/t_trace_ena_cc.out

@@ -0,0 +1,89 @@
+$version Generated by VerilatedVcd $end
+$date Sat Jan 27 15:03:24 2018
+ $end
+$timescale   1ns $end
+
+ $scope module top $end
+  $var wire  1 ' clk $end
+  $scope module t $end
+   $var wire 32 $ c_trace_on [31:0] $end
+   $var wire  1 ' clk $end
+   $var wire 32 # cyc [31:0] $end
+   $var real 64 % r $end
+  $upscope $end
+ $upscope $end
+$enddefinitions $end
+
+
+#0
+b00000000000000000000000000000001 #
+b00000000000000000000000000000000 $
+r0 %
+0'
+#10
+b00000000000000000000000000000010 #
+r0.1 %
+1'
+#15
+0'
+#20
+b00000000000000000000000000000011 #
+b00000000000000000000000000000001 $
+r0.2 %
+1'
+#25
+0'
+#30
+b00000000000000000000000000000100 #
+b00000000000000000000000000000010 $
+r0.3 %
+1'
+#35
+0'
+#40
+b00000000000000000000000000000101 #
+b00000000000000000000000000000011 $
+r0.4 %
+1'
+#45
+0'
+#50
+b00000000000000000000000000000110 #
+b00000000000000000000000000000100 $
+r0.5 %
+1'
+#55
+0'
+#60
+b00000000000000000000000000000111 #
+b00000000000000000000000000000101 $
+r0.6 %
+1'
+#65
+0'
+#70
+b00000000000000000000000000001000 #
+b00000000000000000000000000000110 $
+r0.7 %
+1'
+#75
+0'
+#80
+b00000000000000000000000000001001 #
+b00000000000000000000000000000111 $
+r0.7999999999999999 %
+1'
+#85
+0'
+#90
+b00000000000000000000000000001010 #
+b00000000000000000000000000001000 $
+r0.8999999999999999 %
+1'
+#95
+0'
+#100
+b00000000000000000000000000001011 #
+b00000000000000000000000000001001 $
+r0.9999999999999999 %
+1'

test_regress/t/t_trace_ena_cc.pl

@@ -10,18 +10,20 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); di
 top_filename("t/t_trace_ena.v");
 
 compile (
-	 verilator_flags2 => ['-trace'],
-	 );
+    verilator_flags2 => ['-trace'],
+    );
 
 execute (
-	 check_finished=>1,
-	 );
+    check_finished=>1,
+    );
 
 if ($Self->{vlt}) {
     file_grep     ("$Self->{obj_dir}/V$Self->{name}__Trace__Slow.cpp", qr/c_trace_on\"/x);
     file_grep_not ("$Self->{obj_dir}/V$Self->{name}__Trace__Slow.cpp", qr/_trace_off\"/x);
     file_grep     ("$Self->{obj_dir}/simx.vcd", qr/\$enddefinitions/x);
     file_grep_not ("$Self->{obj_dir}/simx.vcd", qr/inside_sub/x);
+
+    vcd_identical("$Self->{obj_dir}/simx.vcd", "t/$Self->{name}.out");
 }
 
 ok(1);

test_regress/t/t_trace_ena_sc.out

@@ -0,0 +1,164 @@
+$version Generated by VerilatedVcd $end
+$date Mon Jan 29 09:34:59 2018
+ $end
+$timescale   1ps $end
+
+ $scope module top $end
+  $scope module t $end
+   $var wire 32 % c_trace_on [31:0] $end
+   $var wire  1 # clk $end
+   $var wire 32 $ cyc [31:0] $end
+   $var real 64 & r $end
+  $upscope $end
+ $upscope $end
+$enddefinitions $end
+
+
+#0
+0#
+b00000000000000000000000000000001 $
+b00000000000000000000000000000000 %
+r0 &
+#10000
+1#
+b00000000000000000000000000000010 $
+r0.1 &
+#11000
+#12000
+#13000
+#14000
+#15000
+0#
+#16000
+#17000
+#18000
+#19000
+#20000
+1#
+b00000000000000000000000000000011 $
+b00000000000000000000000000000001 %
+r0.2 &
+#21000
+#22000
+#23000
+#24000
+#25000
+0#
+#26000
+#27000
+#28000
+#29000
+#30000
+1#
+b00000000000000000000000000000100 $
+b00000000000000000000000000000010 %
+r0.3 &
+#31000
+#32000
+#33000
+#34000
+#35000
+0#
+#36000
+#37000
+#38000
+#39000
+#40000
+1#
+b00000000000000000000000000000101 $
+b00000000000000000000000000000011 %
+r0.4 &
+#41000
+#42000
+#43000
+#44000
+#45000
+0#
+#46000
+#47000
+#48000
+#49000
+#50000
+1#
+b00000000000000000000000000000110 $
+b00000000000000000000000000000100 %
+r0.5 &
+#51000
+#52000
+#53000
+#54000
+#55000
+0#
+#56000
+#57000
+#58000
+#59000
+#60000
+1#
+b00000000000000000000000000000111 $
+b00000000000000000000000000000101 %
+r0.6 &
+#61000
+#62000
+#63000
+#64000
+#65000
+0#
+#66000
+#67000
+#68000
+#69000
+#70000
+1#
+b00000000000000000000000000001000 $
+b00000000000000000000000000000110 %
+r0.7 &
+#71000
+#72000
+#73000
+#74000
+#75000
+0#
+#76000
+#77000
+#78000
+#79000
+#80000
+1#
+b00000000000000000000000000001001 $
+b00000000000000000000000000000111 %
+r0.7999999999999999 &
+#81000
+#82000
+#83000
+#84000
+#85000
+0#
+#86000
+#87000
+#88000
+#89000
+#90000
+1#
+b00000000000000000000000000001010 $
+b00000000000000000000000000001000 %
+r0.8999999999999999 &
+#91000
+#92000
+#93000
+#94000
+#95000
+0#
+#96000
+#97000
+#98000
+#99000
+#100000
+1#
+b00000000000000000000000000001011 $
+b00000000000000000000000000001001 %
+r0.9999999999999999 &
+#101000
+#102000
+#103000
+#104000

test_regress/t/t_trace_ena_sc.pl

@@ -10,16 +10,18 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); di
 top_filename("t/t_trace_ena.v");
 
 compile (
-	 verilator_flags2 => ['-trace -sc'],
-	 );
+    verilator_flags2 => ['-trace -sc'],
+    );
 
 execute (
-	 check_finished=>1,
-	 );
+    check_finished=>1,
+    );
 
 if ($Self->{vlt}) {
     # Note more checks in _cc.pl
     file_grep     ("$Self->{obj_dir}/simx.vcd", qr/\$enddefinitions/x);
+
+    vcd_identical("$Self->{obj_dir}/simx.vcd", "t/$Self->{name}.out");
 }
 
 ok(1);