diff --git a/Changes b/Changes
index 7bca6829d..9ded95c50 100644
--- a/Changes
+++ b/Changes
@@ -34,6 +34,8 @@ The contributors that suggested a given feature are shown in []. Thanks!
 
 ****  Fix labels on functions with returns, bug1614. [Mitch Hayenga]
 
+****  Fix false unused message on __Vemumtab, msg3180. [Tobias Rosenkranz]
+
 
 * Verilator 4.022 2019-11-10
 
diff --git a/src/V3Undriven.cpp b/src/V3Undriven.cpp
index db01e5f05..2c9e3b308 100644
--- a/src/V3Undriven.cpp
+++ b/src/V3Undriven.cpp
@@ -292,6 +292,9 @@ private:
                 || (m_taskp && (m_taskp->dpiImport() || m_taskp->dpiExport()))) {
                 entryp->usedWhole();
             }
+            if (nodep->valuep()) {
+                entryp->drivenWhole();
+            }
         }
         // Discover variables used in bit definitions, etc
         iterateChildren(nodep);
diff --git a/test_regress/t/t_bug3180.pl b/test_regress/t/t_bug3180.pl
new file mode 100755
index 000000000..5fb3165c1
--- /dev/null
+++ b/test_regress/t/t_bug3180.pl
@@ -0,0 +1,17 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2019 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+
+scenarios(simulator => 1);
+
+compile(
+    verilator_flags2 => ['-Wall -Wno-DECLFILENAME --coverage-line'],
+    );
+
+ok(1);
+1;
diff --git a/test_regress/t/t_bug3180.v b/test_regress/t/t_bug3180.v
new file mode 100644
index 000000000..e5a2561d9
--- /dev/null
+++ b/test_regress/t/t_bug3180.v
@@ -0,0 +1,51 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2019 by Wilson Snyder.
+
+module t
+  (/*AUTOARG*/
+   // Outputs
+   someOutput,
+   // Inputs
+   clk, reset_l, InOne, InTwo
+   );
+
+   input         clk;
+   input         reset_l;
+   input         InOne, InTwo;
+   output logic  someOutput;
+
+   typedef enum {
+                 STATE_ONE,
+                 STATE_TWO,
+                 STATE_THREE,
+                 STATE_FOUR
+                 } some_state_t;
+
+   some_state_t some_FSM;
+
+   always_ff @ (posedge clk or negedge reset_l) begin
+      if(!reset_l)
+        some_FSM <= some_FSM.first;
+      else begin
+         unique case (some_FSM)
+           STATE_ONE, STATE_TWO, STATE_THREE: begin
+              if(InOne & InTwo)
+                some_FSM <= some_FSM.next;
+              else if(InOne)
+                some_FSM <= some_FSM;
+              else
+                some_FSM <= some_FSM.first;
+           end
+           default: begin
+              some_FSM <= STATE_ONE;
+           end
+         endcase
+      end
+   end
+
+   always_comb begin
+      someOutput = (some_FSM == STATE_FOUR);
+   end
+endmodule