Mario1159/verilator
1
0
Fork 0
forked from github/verilator
Code Pull Requests Releases 1 Activity

In warnings, rename cells to instances to match IEEE

Browse Source
This commit is contained in:
Wilson Snyder 2020-12-12 22:43:55 -05:00
parent 53c4c7d540
commit b04a1caeac
18 changed files with 84 additions and 83 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

81
bin/verilator
View File

@ -1639,8 +1639,8 @@ into Verilator. (Similar to perl -V.) See also --getenv.
=item -v I<filename> =item -v I<filename>
Read the filename as a Verilog library. Any modules in the file may be Read the filename as a Verilog library. Any modules in the file may be
used to resolve cell instantiations in the top level module, else ignored. used to resolve instances in the top level module, else ignored. Note -v
Note -v is fairly standard across Verilog tools. is fairly standard across Verilog tools.
=item --no-verilate =item --no-verilate
@ -3104,8 +3104,8 @@ Enable/disable waveform tracing for all future signals declared in the
specified filename (or wildcard with '*' or '?', or all files if omitted) specified filename (or wildcard with '*' or '?', or all files if omitted)
and range of line numbers (or all lines if omitted). and range of line numbers (or all lines if omitted).
For tracing_off, cells below any module in the files/ranges specified will For tracing_off, instances below any module in the files/ranges specified
also not be traced. will also not be traced.
=item clock_enable -module "<modulename>" -var "<signame>" =item clock_enable -module "<modulename>" -var "<signame>"
@ -3777,13 +3777,13 @@ for use by downstream applications.
=item /*verilator tracing_off*/ =item /*verilator tracing_off*/
Disable waveform tracing for all future signals that are declared in this Disable waveform tracing for all future signals that are declared in this
module, or cells below this module. Often this is placed just after a module, or instances below this module. Often this is placed just after a
primitive's module statement, so that the entire module and cells below it primitive's module statement, so that the entire module and instances below
are not traced. it are not traced.
=item /*verilator tracing_on*/ =item /*verilator tracing_on*/
Re-enable waveform tracing for all future signals or cells that are Re-enable waveform tracing for all future signals or instances that are
declared. declared.
=back =back
@ -3837,8 +3837,8 @@ for example a[2].b is acceptable, while a[x].b is generally not.
References into generated and arrayed instances use the instance names References into generated and arrayed instances use the instance names
specified in the Verilog standard; arrayed instances are named specified in the Verilog standard; arrayed instances are named
{cellName}[{instanceNumber}] in Verilog, which becomes {instanceName}[{instanceNumber}] in Verilog, which becomes
{cellname}__BRA__{instanceNumber}__KET__ inside the generated C++ code. {instanceName}__BRA__{instanceNumber}__KET__ inside the generated C++ code.
=head2 Latches =head2 Latches
@ -4523,9 +4523,9 @@ top module statement is processed.
Warns that a wire is being implicitly declared (it is a single bit wide Warns that a wire is being implicitly declared (it is a single bit wide
output from a sub-module.) While legal in Verilog, implicit declarations output from a sub-module.) While legal in Verilog, implicit declarations
only work for single bit wide signals (not buses), do not allow using a only work for single bit wide signals (not buses), do not allow using a
signal before it is implicitly declared by a cell, and can lead to dangling signal before it is implicitly declared by an instance, and can lead to
nets. A better option is the /*AUTOWIRE*/ feature of Verilog-Mode for dangling nets. A better option is the /*AUTOWIRE*/ feature of Verilog-Mode
Emacs, available from L<https://www.veripool.org/verilog-mode> for Emacs, available from L<https://www.veripool.org/verilog-mode>
Ignoring this warning will only suppress the lint check, it will simulate Ignoring this warning will only suppress the lint check, it will simulate
correctly. correctly.
@ -4598,10 +4598,10 @@ Warns that a packed vector is declared with little endian bit numbering
and little numbering is now thus often due to simple oversight instead of and little numbering is now thus often due to simple oversight instead of
intent. intent.
Also warns that a cell is declared with little endian range (i.e. [0:7] or Also warns that an instance is declared with little endian range
[7]) and is connected to a N-wide signal. Based on IEEE the bits will (i.e. [0:7] or [7]) and is connected to a N-wide signal. Based on IEEE the
likely be backwards from what you expect (i.e. cell [0] will connect to bits will likely be backwards from what you expect (i.e. instance [0] will
signal bit [N-1] not bit [0]). connect to signal bit [N-1] not bit [0]).
Ignoring this warning will only suppress the lint check, it will simulate Ignoring this warning will only suppress the lint check, it will simulate
correctly. correctly.
@ -4633,10 +4633,10 @@ instantiated by any other module, and both modules were put on the command
line (not in a library). Three likely cases: line (not in a library). Three likely cases:
1. A single module is intended to be the top. This warning then occurs 1. A single module is intended to be the top. This warning then occurs
because some low level cell is being read in, but is not really needed as because some low level instance is being read in, but is not really needed
part of the design. The best solution for this situation is to ensure that as part of the design. The best solution for this situation is to ensure
only the top module is put on the command line without any flags, and all that only the top module is put on the command line without any flags, and
remaining library files are read in as libraries with -v, or are all remaining library files are read in as libraries with -v, or are
automatically resolved by having filenames that match the module names. automatically resolved by having filenames that match the module names.
2. A single module is intended to be the top, the name of it is known, and 2. A single module is intended to be the top, the name of it is known, and
@ -4656,27 +4656,26 @@ identical, e.g. multiple modules with a "clk" input.
=item PINCONNECTEMPTY =item PINCONNECTEMPTY
Warns that a cell instantiation has a pin which is connected to Warns that an instance has a pin which is connected to .pin_name(),
.pin_name(), e.g. not another signal, but with an explicit mention of the e.g. not another signal, but with an explicit mention of the pin. It may
pin. It may be desirable to disable PINCONNECTEMPTY, as this indicates be desirable to disable PINCONNECTEMPTY, as this indicates intention to
intention to have a no-connect. have a no-connect.
Disabled by default as this is a code style warning; it will simulate Disabled by default as this is a code style warning; it will simulate
correctly. correctly.
=item PINMISSING =item PINMISSING
Warns that a module has a pin which is not mentioned in a cell Warns that a module has a pin which is not mentioned in an instance. If a
instantiation. If a pin is not missing it should still be specified on the pin is not missing it should still be specified on the instance declaration
cell declaration with a empty connection, using "(.pin_name())". with a empty connection, using "(.pin_name())".
Ignoring this warning will only suppress the lint check, it will simulate Ignoring this warning will only suppress the lint check, it will simulate
correctly. correctly.
=item PINNOCONNECT =item PINNOCONNECT
Warns that a cell instantiation has a pin which is not connected to another Warns that an instance has a pin which is not connected to another signal.
signal.
Disabled by default as this is a code style warning; it will simulate Disabled by default as this is a code style warning; it will simulate
correctly. correctly.
@ -4919,7 +4918,7 @@ potentially resolving the conflict. If you run with --report-unoptflat
Verilator will suggest possible candidates for C<split_var>. Verilator will suggest possible candidates for C<split_var>.
The UNOPTFLAT warning may also be due to clock enables, identified from the The UNOPTFLAT warning may also be due to clock enables, identified from the
reported path going through a clock gating cell. To fix these, use the reported path going through a clock gating instance. To fix these, use the
clock_enable meta comment described above. clock_enable meta comment described above.
The UNOPTFLAT warning may also occur where outputs from a block of logic The UNOPTFLAT warning may also occur where outputs from a block of logic
@ -5494,21 +5493,21 @@ by your code or you'll get strange results.
=item Should a module be in Verilog or SystemC? =item Should a module be in Verilog or SystemC?
Sometimes there is a block that just interconnects cells, and have a choice Sometimes there is a block that just interconnects instances, and have a
as to if you write it in Verilog or SystemC. Everything else being equal, choice as to if you write it in Verilog or SystemC. Everything else being
best performance is when Verilator sees all of the design. So, look at the equal, best performance is when Verilator sees all of the design. So, look
hierarchy of your design, labeling cells as to if they are SystemC or at the hierarchy of your design, labeling instances as to if they are
Verilog. Then: SystemC or Verilog. Then:
A module with only SystemC cells below must be SystemC. A module with only SystemC instances below must be SystemC.
A module with a mix of Verilog and SystemC cells below must be SystemC. (As A module with a mix of Verilog and SystemC instances below must be
Verilator cannot connect to lower-level SystemC cells.) SystemC. (As Verilator cannot connect to lower-level SystemC instances.)
A module with only Verilog cells below can be either, but for best A module with only Verilog instances below can be either, but for best
performance should be Verilog. (The exception is if you have a design that performance should be Verilog. (The exception is if you have a design that
is instantiated many times; in this case Verilating one of the lower is instantiated many times; in this case Verilating one of the lower
modules and instantiating that Verilated cells multiple times into a modules and instantiating that Verilated instances multiple times into a
SystemC module *may* be faster.) SystemC module *may* be faster.)
=back =back

2
src/V3AstNodes.h
View File

@ -2940,7 +2940,7 @@ public:
AstBind(FileLine* fl, const string& name, AstNode* cellsp) AstBind(FileLine* fl, const string& name, AstNode* cellsp)
: ASTGEN_SUPER(fl) : ASTGEN_SUPER(fl)
, m_name{name} { , m_name{name} {
UASSERT_OBJ(VN_IS(cellsp, Cell), cellsp, "Only cells allowed to be bound"); UASSERT_OBJ(VN_IS(cellsp, Cell), cellsp, "Only instances allowed to be bound");
addNOp1p(cellsp); addNOp1p(cellsp);
} }
ASTNODE_NODE_FUNCS(Bind) ASTNODE_NODE_FUNCS(Bind)

2
src/V3Descope.cpp
View File

@ -123,7 +123,7 @@ private:
hierUnprot = v3Global.opt.modPrefix() + "_"; // Prefix before protected part hierUnprot = v3Global.opt.modPrefix() + "_"; // Prefix before protected part
return scopep->modp()->name() + "::"; return scopep->modp()->name() + "::";
} else if (relativeRefOk && scopep->aboveScopep() && scopep->aboveScopep() == m_scopep) { } else if (relativeRefOk && scopep->aboveScopep() && scopep->aboveScopep() == m_scopep) {
// Reference to scope of cell directly under this module, can just "cell->" // Reference to scope of instance directly under this module, can just "cell->"
string name = scopep->name(); string name = scopep->name();
string::size_type pos; string::size_type pos;
if ((pos = name.rfind('.')) != string::npos) name.erase(0, pos + 1); if ((pos = name.rfind('.')) != string::npos) name.erase(0, pos + 1);

2
src/V3Inline.cpp
View File

@ -614,7 +614,7 @@ public:
// CONSTRUCTORS // CONSTRUCTORS
explicit InlineVisitor(AstNode* nodep) { iterate(nodep); } explicit InlineVisitor(AstNode* nodep) { iterate(nodep); }
virtual ~InlineVisitor() override { // virtual ~InlineVisitor() override { //
V3Stats::addStat("Optimizations, Inlined cells", m_statCells); V3Stats::addStat("Optimizations, Inlined instances", m_statCells);
} }
}; };

4
src/V3Inst.cpp
View File

@ -341,8 +341,8 @@ private:
// Arrayed instants: one bit for each of the instants (each // Arrayed instants: one bit for each of the instants (each
// assign is 1 pinwidth wide) // assign is 1 pinwidth wide)
if (m_cellRangep->littleEndian()) { if (m_cellRangep->littleEndian()) {
nodep->exprp()->v3warn(LITENDIAN, "Little endian cell range connecting to " nodep->exprp()->v3warn(LITENDIAN, "Little endian instance range connecting to "
"vector: left < right of cell range: [" "vector: left < right of instance range: ["
<< m_cellRangep->leftConst() << ":" << m_cellRangep->leftConst() << ":"
<< m_cellRangep->rightConst() << "]"); << m_cellRangep->rightConst() << "]");
} }

6
src/V3LinkCells.cpp
View File

@ -183,7 +183,7 @@ private:
} }
v3error("Specified --top-module '" v3error("Specified --top-module '"
<< v3Global.opt.topModule() << v3Global.opt.topModule()
<< "' isn't at the top level, it's under another cell '" << "' isn't at the top level, it's under another instance '"
<< (abovep ? abovep->prettyName() : "UNKNOWN") << "'"); << (abovep ? abovep->prettyName() : "UNKNOWN") << "'");
} }
} }
@ -363,7 +363,7 @@ private:
for (AstPin *nextp, *pinp = nodep->pinsp(); pinp; pinp = nextp) { for (AstPin *nextp, *pinp = nodep->pinsp(); pinp; pinp = nextp) {
nextp = VN_CAST(pinp->nextp(), Pin); nextp = VN_CAST(pinp->nextp(), Pin);
if (pinp->dotStar()) { if (pinp->dotStar()) {
if (pinStar) pinp->v3error("Duplicate .* in a cell"); if (pinStar) pinp->v3error("Duplicate .* in an instance");
pinStar = true; pinStar = true;
// Done with this fake pin // Done with this fake pin
VL_DO_DANGLING(pinp->unlinkFrBack()->deleteTree(), pinp); VL_DO_DANGLING(pinp->unlinkFrBack()->deleteTree(), pinp);
@ -383,7 +383,7 @@ private:
std::unordered_set<string> ports; // Symbol table of all connected port names std::unordered_set<string> ports; // Symbol table of all connected port names
for (AstPin* pinp = nodep->pinsp(); pinp; pinp = VN_CAST(pinp->nextp(), Pin)) { for (AstPin* pinp = nodep->pinsp(); pinp; pinp = VN_CAST(pinp->nextp(), Pin)) {
if (pinp->name() == "") if (pinp->name() == "")
pinp->v3error("Connect by position is illegal in .* connected cells"); pinp->v3error("Connect by position is illegal in .* connected instances");
if (!pinp->exprp()) { if (!pinp->exprp()) {
if (pinp->name().substr(0, 11) == "__pinNumber") { if (pinp->name().substr(0, 11) == "__pinNumber") {
pinp->v3warn(PINNOCONNECT, pinp->v3warn(PINNOCONNECT,

27
src/V3LinkDot.cpp
View File

@ -225,7 +225,7 @@ public:
if (VN_IS(nodep, Var)) { if (VN_IS(nodep, Var)) {
return "variable"; return "variable";
} else if (VN_IS(nodep, Cell)) { } else if (VN_IS(nodep, Cell)) {
return "cell"; return "instance";
} else if (VN_IS(nodep, Task)) { } else if (VN_IS(nodep, Task)) {
return "task"; return "task";
} else if (VN_IS(nodep, Func)) { } else if (VN_IS(nodep, Func)) {
@ -459,7 +459,7 @@ public:
ifacerefp->v3fatalSrc("Unlinked interface"); ifacerefp->v3fatalSrc("Unlinked interface");
} }
} else if (ifacerefp->ifaceViaCellp()->dead()) { } else if (ifacerefp->ifaceViaCellp()->dead()) {
ifacerefp->v3error("Parent cell's interface is not found: " ifacerefp->v3error("Parent instance's interface is not found: "
<< AstNode::prettyNameQ(ifacerefp->ifaceName())); << AstNode::prettyNameQ(ifacerefp->ifaceName()));
continue; continue;
} }
@ -795,7 +795,7 @@ class LinkDotFindVisitor final : public AstNVisitor {
<< AstNode::prettyNameQ(nodep->origName())); << AstNode::prettyNameQ(nodep->origName()));
} else if (doit) { } else if (doit) {
UINFO(4, " Link Module: " << nodep << endl); UINFO(4, " Link Module: " << nodep << endl);
UASSERT_OBJ(!nodep->dead(), nodep, "Module in cell tree mislabeled as dead?"); UASSERT_OBJ(!nodep->dead(), nodep, "Module in instance tree mislabeled as dead?");
VSymEnt* upperSymp = m_curSymp ? m_curSymp : m_statep->rootEntp(); VSymEnt* upperSymp = m_curSymp ? m_curSymp : m_statep->rootEntp();
AstPackage* pkgp = VN_CAST(nodep, Package); AstPackage* pkgp = VN_CAST(nodep, Package);
m_classOrPackagep = pkgp; m_classOrPackagep = pkgp;
@ -898,8 +898,8 @@ class LinkDotFindVisitor final : public AstNVisitor {
VSymEnt* okSymp; VSymEnt* okSymp;
aboveSymp = m_statep->findDotted(nodep->fileline(), aboveSymp, scope, baddot, okSymp); aboveSymp = m_statep->findDotted(nodep->fileline(), aboveSymp, scope, baddot, okSymp);
UASSERT_OBJ(aboveSymp, nodep, UASSERT_OBJ(aboveSymp, nodep,
"Can't find cell insertion point at " << AstNode::prettyNameQ(baddot) "Can't find instance insertion point at "
<< " in: " << nodep->prettyNameQ()); << AstNode::prettyNameQ(baddot) << " in: " << nodep->prettyNameQ());
} }
{ {
m_scope = m_scope + "." + nodep->name(); m_scope = m_scope + "." + nodep->name();
@ -1399,7 +1399,7 @@ private:
VSymEnt* foundp = m_statep->getNodeSym(nodep)->findIdFallback(nodep->path()); VSymEnt* foundp = m_statep->getNodeSym(nodep)->findIdFallback(nodep->path());
AstCell* cellp = foundp ? VN_CAST(foundp->nodep(), Cell) : nullptr; AstCell* cellp = foundp ? VN_CAST(foundp->nodep(), Cell) : nullptr;
if (!cellp) { if (!cellp) {
nodep->v3error("In defparam, cell " << nodep->path() << " never declared"); nodep->v3error("In defparam, instance " << nodep->path() << " never declared");
} else { } else {
AstNode* exprp = nodep->rhsp()->unlinkFrBack(); AstNode* exprp = nodep->rhsp()->unlinkFrBack();
UINFO(9, "Defparam cell " << nodep->path() << "." << nodep->name() << " attach-to " UINFO(9, "Defparam cell " << nodep->path() << "." << nodep->name() << " attach-to "
@ -1558,9 +1558,10 @@ class LinkDotScopeVisitor final : public AstNVisitor {
VSymEnt* okSymp; VSymEnt* okSymp;
VSymEnt* cellSymp = m_statep->findDotted(nodep->fileline(), m_modSymp, ifcellname, VSymEnt* cellSymp = m_statep->findDotted(nodep->fileline(), m_modSymp, ifcellname,
baddot, okSymp); baddot, okSymp);
UASSERT_OBJ(cellSymp, nodep, UASSERT_OBJ(
"No symbol for interface cell: " << nodep->prettyNameQ(ifcellname)); cellSymp, nodep,
UINFO(5, " Found interface cell: se" << cvtToHex(cellSymp) << " " "No symbol for interface instance: " << nodep->prettyNameQ(ifcellname));
UINFO(5, " Found interface instance: se" << cvtToHex(cellSymp) << " "
<< cellSymp->nodep() << endl); << cellSymp->nodep() << endl);
if (dtypep->modportName() != "") { if (dtypep->modportName() != "") {
VSymEnt* mpSymp = m_statep->findDotted(nodep->fileline(), m_modSymp, VSymEnt* mpSymp = m_statep->findDotted(nodep->fileline(), m_modSymp,
@ -2007,7 +2008,7 @@ private:
checkNoDot(nodep); checkNoDot(nodep);
iterateChildren(nodep); iterateChildren(nodep);
if (!nodep->modVarp()) { if (!nodep->modVarp()) {
UASSERT_OBJ(m_pinSymp, nodep, "Pin not under cell?"); UASSERT_OBJ(m_pinSymp, nodep, "Pin not under instance?");
VSymEnt* foundp = m_pinSymp->findIdFlat(nodep->name()); VSymEnt* foundp = m_pinSymp->findIdFlat(nodep->name());
const char* whatp = nodep->param() ? "parameter pin" : "pin"; const char* whatp = nodep->param() ? "parameter pin" : "pin";
if (!foundp) { if (!foundp) {
@ -2345,7 +2346,7 @@ private:
<< modportp->prettyNameQ()); << modportp->prettyNameQ());
} else { } else {
AstCell* cellp = VN_CAST(m_ds.m_dotSymp->nodep(), Cell); AstCell* cellp = VN_CAST(m_ds.m_dotSymp->nodep(), Cell);
UASSERT_OBJ(cellp, nodep, "Modport not referenced from a cell"); UASSERT_OBJ(cellp, nodep, "Modport not referenced from an instance");
VSymEnt* cellEntp = m_statep->getNodeSym(cellp); VSymEnt* cellEntp = m_statep->getNodeSym(cellp);
UASSERT_OBJ(cellEntp, nodep, "No interface sym entry"); UASSERT_OBJ(cellEntp, nodep, "No interface sym entry");
VSymEnt* parentEntp = cellEntp->parentp(); // Container of the var; probably a VSymEnt* parentEntp = cellEntp->parentp(); // Container of the var; probably a
@ -2751,8 +2752,8 @@ private:
if (nodep->user3SetOnce()) return; if (nodep->user3SetOnce()) return;
if (m_ds.m_dotPos if (m_ds.m_dotPos
== DP_SCOPE) { // Already under dot, so this is {modulepart} DOT {modulepart} == DP_SCOPE) { // Already under dot, so this is {modulepart} DOT {modulepart}
nodep->v3error("Syntax Error: Range ':', '+:' etc are not allowed in the cell part of " nodep->v3error("Syntax Error: Range ':', '+:' etc are not allowed in the instance "
"a dotted reference"); "part of a dotted reference");
m_ds.m_dotErr = true; m_ds.m_dotErr = true;
return; return;
} }

5
src/V3ParseGrammar.cpp
View File

@ -95,14 +95,15 @@ AstRange* V3ParseGrammar::scrubRange(AstNodeRange* nrangep) {
nextp = VN_CAST(nodep->nextp(), NodeRange); nextp = VN_CAST(nodep->nextp(), NodeRange);
if (!VN_IS(nodep, Range)) { if (!VN_IS(nodep, Range)) {
nodep->v3error( nodep->v3error(
"Unsupported or syntax error: Unsized range in cell or other declaration"); "Unsupported or syntax error: Unsized range in instance or other declaration");
nodep->unlinkFrBack(); nodep->unlinkFrBack();
VL_DO_DANGLING(nodep->deleteTree(), nodep); VL_DO_DANGLING(nodep->deleteTree(), nodep);
} }
} }
if (nrangep && nrangep->nextp()) { if (nrangep && nrangep->nextp()) {
// Not supported by at least 2 of big 3 // Not supported by at least 2 of big 3
nrangep->nextp()->v3warn(E_UNSUPPORTED, "Unsupported: Multidimensional cells/interfaces."); nrangep->nextp()->v3warn(E_UNSUPPORTED,
"Unsupported: Multidimensional instances/interfaces.");
nrangep->nextp()->unlinkFrBackWithNext()->deleteTree(); nrangep->nextp()->unlinkFrBackWithNext()->deleteTree();
} }
return VN_CAST(nrangep, Range); return VN_CAST(nrangep, Range);

2
src/V3SymTable.h
View File

@ -267,7 +267,7 @@ public:
scopes += AstNode::prettyName(it->first); scopes += AstNode::prettyName(it->first);
} }
} }
if (scopes == "") scopes = "<no cells found>"; if (scopes == "") scopes = "<no instances found>";
std::cerr << V3Error::warnMore() << "... Known scopes under '" << prettyName std::cerr << V3Error::warnMore() << "... Known scopes under '" << prettyName
<< "': " << scopes << endl; << "': " << scopes << endl;
if (debug()) dump(std::cerr, " KnownScope: ", 1); if (debug()) dump(std::cerr, " KnownScope: ", 1);

2
src/V3TraceDecl.cpp
View File

@ -59,7 +59,7 @@ private:
if (!varp->isTrace()) { if (!varp->isTrace()) {
return "Verilator trace_off"; return "Verilator trace_off";
} else if (!nodep->isTrace()) { } else if (!nodep->isTrace()) {
return "Verilator cell trace_off"; return "Verilator instance trace_off";
} else if (!v3Global.opt.traceUnderscore()) { } else if (!v3Global.opt.traceUnderscore()) {
const string prettyName = varp->prettyName(); const string prettyName = varp->prettyName();
if (!prettyName.empty() && prettyName[0] == '_') return "Leading underscore"; if (!prettyName.empty() && prettyName[0] == '_') return "Leading underscore";

2
test_regress/t/t_flag_topmod2_bad.out
View File

@ -1,2 +1,2 @@
%Error: Specified --top-module 'a' isn't at the top level, it's under another cell 'a_top' %Error: Specified --top-module 'a' isn't at the top level, it's under another instance 'a_top'
%Error: Exiting due to %Error: Exiting due to

8
test_regress/t/t_interface_array_nocolon_bad.out
View File

@ -1,17 +1,17 @@
%Warning-LITENDIAN: t/t_interface_array_nocolon_bad.v:26:26: Little endian cell range connecting to vector: left < right of cell range: [0:2] %Warning-LITENDIAN: t/t_interface_array_nocolon_bad.v:26:26: Little endian instance range connecting to vector: left < right of instance range: [0:2]
: ... In instance t : ... In instance t
26 | foo_intf foos [N] (.x(X)); 26 | foo_intf foos [N] (.x(X));
| ^ | ^
... Use "/* verilator lint_off LITENDIAN */" and lint_on around source to disable this message. ... Use "/* verilator lint_off LITENDIAN */" and lint_on around source to disable this message.
%Warning-LITENDIAN: t/t_interface_array_nocolon_bad.v:27:28: Little endian cell range connecting to vector: left < right of cell range: [1:3] %Warning-LITENDIAN: t/t_interface_array_nocolon_bad.v:27:28: Little endian instance range connecting to vector: left < right of instance range: [1:3]
: ... In instance t : ... In instance t
27 | foo_intf fool [1:3] (.x(X)); 27 | foo_intf fool [1:3] (.x(X));
| ^ | ^
%Warning-LITENDIAN: t/t_interface_array_nocolon_bad.v:30:26: Little endian cell range connecting to vector: left < right of cell range: [0:2] %Warning-LITENDIAN: t/t_interface_array_nocolon_bad.v:30:26: Little endian instance range connecting to vector: left < right of instance range: [0:2]
: ... In instance t : ... In instance t
30 | foo_subm subs [N] (.x(X)); 30 | foo_subm subs [N] (.x(X));
| ^ | ^
%Warning-LITENDIAN: t/t_interface_array_nocolon_bad.v:31:28: Little endian cell range connecting to vector: left < right of cell range: [1:3] %Warning-LITENDIAN: t/t_interface_array_nocolon_bad.v:31:28: Little endian instance range connecting to vector: left < right of instance range: [1:3]
: ... In instance t : ... In instance t
31 | foo_subm subl [1:3] (.x(X)); 31 | foo_subm subl [1:3] (.x(X));
| ^ | ^

2
test_regress/t/t_interface_mismodport_bad.out
View File

@ -1,5 +1,5 @@
%Error: t/t_interface_mismodport_bad.v:36:12: Can't find definition of 'bad' in dotted signal: 'isub.bad' %Error: t/t_interface_mismodport_bad.v:36:12: Can't find definition of 'bad' in dotted signal: 'isub.bad'
36 | isub.bad = i_value; 36 | isub.bad = i_value;
| ^~~ | ^~~
... Known scopes under 'bad': <no cells found> ... Known scopes under 'bad': <no instances found>
%Error: Exiting due to %Error: Exiting due to

2
test_regress/t/t_interface_top_bad.out
View File

@ -1,7 +1,7 @@
%Error-UNSUPPORTED: t/t_interface_top_bad.v:17:19: Unsupported: Interfaced port on top level module %Error-UNSUPPORTED: t/t_interface_top_bad.v:17:19: Unsupported: Interfaced port on top level module
17 | ifc.counter_mp c_data 17 | ifc.counter_mp c_data
| ^~~~~~ | ^~~~~~
%Error: t/t_interface_top_bad.v:17:4: Parent cell's interface is not found: 'ifc' %Error: t/t_interface_top_bad.v:17:4: Parent instance's interface is not found: 'ifc'
17 | ifc.counter_mp c_data 17 | ifc.counter_mp c_data
| ^~~ | ^~~
%Error: Exiting due to %Error: Exiting due to

2
test_regress/t/t_interface_typo_bad.out
View File

@ -1,4 +1,4 @@
%Error: t/t_interface_typo_bad.v:14:4: Parent cell's interface is not found: 'foo_intf' %Error: t/t_interface_typo_bad.v:14:4: Parent instance's interface is not found: 'foo_intf'
14 | foo_intf foo 14 | foo_intf foo
| ^~~~~~~~ | ^~~~~~~~
%Error: t/t_interface_typo_bad.v:22:4: Cannot find file containing interface: 'fo_intf' %Error: t/t_interface_typo_bad.v:22:4: Cannot find file containing interface: 'fo_intf'

4
test_regress/t/t_mod_interface_array3.out
View File

@ -1,7 +1,7 @@
%Error-UNSUPPORTED: t/t_mod_interface_array3.v:25:20: Unsupported: Multidimensional cells/interfaces. %Error-UNSUPPORTED: t/t_mod_interface_array3.v:25:20: Unsupported: Multidimensional instances/interfaces.
25 | a_if iface [2:0][1:0]; 25 | a_if iface [2:0][1:0];
| ^ | ^
%Error-UNSUPPORTED: t/t_mod_interface_array3.v:27:18: Unsupported: Multidimensional cells/interfaces. %Error-UNSUPPORTED: t/t_mod_interface_array3.v:27:18: Unsupported: Multidimensional instances/interfaces.
27 | sub i_sub[2:0][1:0] (.s(str)); 27 | sub i_sub[2:0][1:0] (.s(str));
| ^ | ^
%Error: Exiting due to %Error: Exiting due to

10
test_regress/t/t_var_bad_sameas.out
View File

@ -1,19 +1,19 @@
%Error: t/t_var_bad_sameas.v:10:8: Unsupported in C: Cell has the same name as variable: 'varfirst' %Error: t/t_var_bad_sameas.v:10:8: Unsupported in C: Instance has the same name as variable: 'varfirst'
10 | sub varfirst (); 10 | sub varfirst ();
| ^~~~~~~~ | ^~~~~~~~
t/t_var_bad_sameas.v:9:12: ... Location of original declaration t/t_var_bad_sameas.v:9:12: ... Location of original declaration
9 | integer varfirst; 9 | integer varfirst;
| ^~~~~~~~ | ^~~~~~~~
%Error: t/t_var_bad_sameas.v:11:9: Unsupported in C: Task has the same name as cell: 'varfirst' %Error: t/t_var_bad_sameas.v:11:9: Unsupported in C: Task has the same name as instance: 'varfirst'
11 | task varfirst; begin end endtask 11 | task varfirst; begin end endtask
| ^~~~~~~~ | ^~~~~~~~
t/t_var_bad_sameas.v:10:8: ... Location of original declaration t/t_var_bad_sameas.v:10:8: ... Location of original declaration
10 | sub varfirst (); 10 | sub varfirst ();
| ^~~~~~~~ | ^~~~~~~~
%Error: t/t_var_bad_sameas.v:14:12: Unsupported in C: Variable has same name as cell: 'cellfirst' %Error: t/t_var_bad_sameas.v:14:12: Unsupported in C: Variable has same name as instance: 'cellfirst'
14 | integer cellfirst; 14 | integer cellfirst;
| ^~~~~~~~~ | ^~~~~~~~~
%Error: t/t_var_bad_sameas.v:15:9: Unsupported in C: Task has the same name as cell: 'cellfirst' %Error: t/t_var_bad_sameas.v:15:9: Unsupported in C: Task has the same name as instance: 'cellfirst'
15 | task cellfirst; begin end endtask 15 | task cellfirst; begin end endtask
| ^~~~~~~~~ | ^~~~~~~~~
t/t_var_bad_sameas.v:13:8: ... Location of original declaration t/t_var_bad_sameas.v:13:8: ... Location of original declaration
@ -22,7 +22,7 @@
%Error: t/t_var_bad_sameas.v:18:12: Unsupported in C: Variable has same name as task: 'taskfirst' %Error: t/t_var_bad_sameas.v:18:12: Unsupported in C: Variable has same name as task: 'taskfirst'
18 | integer taskfirst; 18 | integer taskfirst;
| ^~~~~~~~~ | ^~~~~~~~~
%Error: t/t_var_bad_sameas.v:19:8: Unsupported in C: Cell has the same name as task: 'taskfirst' %Error: t/t_var_bad_sameas.v:19:8: Unsupported in C: Instance has the same name as task: 'taskfirst'
19 | sub taskfirst (); 19 | sub taskfirst ();
| ^~~~~~~~~ | ^~~~~~~~~
t/t_var_bad_sameas.v:17:9: ... Location of original declaration t/t_var_bad_sameas.v:17:9: ... Location of original declaration

2
test_regress/t/t_var_dotted_dup_bad.out
View File

@ -1,4 +1,4 @@
%Error: t/t_var_dotted_dup_bad.v:14:18: Duplicate declaration of cell: 'dccm_bank' %Error: t/t_var_dotted_dup_bad.v:14:18: Duplicate declaration of instance: 'dccm_bank'
14 | eh2_ram dccm_bank (.*); 14 | eh2_ram dccm_bank (.*);
| ^~~~~~~~~ | ^~~~~~~~~
t/t_var_dotted_dup_bad.v:11:18: ... Location of original declaration t/t_var_dotted_dup_bad.v:11:18: ... Location of original declaration