forked from github/verilator
Lint check posedge of nonintegral
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@ -5496,9 +5496,15 @@ private:
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VL_DO_DANGLING(nodep->deleteTree(), nodep);
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VL_DO_DANGLING(nodep->deleteTree(), nodep);
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} else {
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} else {
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userIterateChildren(nodep, WidthVP{SELF, BOTH}.p());
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userIterateChildren(nodep, WidthVP{SELF, BOTH}.p());
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if (nodep->edgeType().anEdge() && nodep->sensp()->dtypep()->skipRefp()->isDouble()) {
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if (nodep->edgeType().anEdge()) {
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nodep->sensp()->v3error(
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AstNodeDType* sensDtp = nodep->sensp()->dtypep()->skipRefp();
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"Edge event control not legal on real type (IEEE 1800-2017 6.12.1)");
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if (sensDtp->isDouble()) {
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nodep->sensp()->v3error(
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"Edge event control not legal on real type (IEEE 1800-2017 6.12.1)");
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} else if (sensDtp->basicp() && !sensDtp->basicp()->keyword().isIntNumeric()) {
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nodep->sensp()->v3error("Edge event control not legal on non-integral type "
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"(IEEE 1800-2017 9.4.2)");
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}
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}
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}
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}
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}
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}
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}
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@ -1,5 +1,9 @@
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%Error: t/t_lint_edge_real_bad.v:16:22: Edge event control not legal on real type (IEEE 1800-2017 6.12.1)
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%Error: t/t_lint_edge_real_bad.v:19:22: Edge event control not legal on real type (IEEE 1800-2017 6.12.1)
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: ... In instance t
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: ... In instance t
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16 | always @ (posedge rbad) $stop;
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19 | always @ (posedge rbad) $stop;
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| ^~~~
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%Error: t/t_lint_edge_real_bad.v:20:22: Edge event control not legal on non-integral type (IEEE 1800-2017 9.4.2)
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: ... In instance t
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20 | always @ (posedge ebad) $stop;
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| ^~~~
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| ^~~~
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%Error: Exiting due to
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%Error: Exiting due to
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@ -10,9 +10,13 @@ module t (/*AUTOARG*/
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);
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);
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input real rbad;
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input real rbad;
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input real rok;
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input real rok;
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event ebad;
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struct packed { int a; } sok;
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always @ (rok) $stop;
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always @ (rok) $stop;
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always @ (sok) $stop;
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always @ (posedge rbad) $stop;
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always @ (posedge rbad) $stop;
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always @ (posedge ebad) $stop;
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endmodule
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endmodule
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