Fix ternary operation with unpacked array, bug1017.

Changes

@@ -39,6 +39,8 @@ indicates the contributor was also the author of the fix; Thanks!
 
 ****  Fix slices of unpacked arrays with non-zero LSBs.
 
+****  Fix ternary operation with unpacked array, bug1017. [Varun Koyyalagunta].
+
 
 * Verilator 3.878 2015-11-01
 

src/V3Slice.cpp

@@ -365,6 +365,8 @@ class SliceVisitor : public AstNVisitor {
 	// The conditional must be a single bit so only look at the expressions
 	nodep->expr1p()->accept(*this);
 	nodep->expr2p()->accept(*this);
+	// Downstream data type may have changed; propagate up
+	nodep->dtypeFrom(nodep->expr1p());
     }
 
     // Return the first AstVarRef under the node
@@ -451,18 +453,6 @@ class SliceVisitor : public AstNVisitor {
 		// Unpacked dimensions are referenced first, make sure we have them all
 		nodep->v3error("Unary operator used across unpacked dimensions");
 	    }
-	    //Dead code
-	    //else if ((int)(dim - (varDim.second)) < 0) {
-	    //	// Implicit packed dimensions are allowed, make them explicit
-	    //	uint32_t newDim = (varDim.second) - dim;
-	    //	AstNode* clonep = nodep->lhsp()->cloneTree(false);
-	    //	clonep->user1p(refp);
-	    //	AstNode* newp = insertImplicit(clonep, dim+1, newDim);
-	    //	nodep->lhsp()->replaceWith(newp); VL_DANGLING(refp);
-	    //	int clones = countClones(nodep->lhsp()->castArraySel());
-	    //	nodep->user2(clones);
-	    //	SliceCloneVisitor scv(nodep);
-	    //}
 	}
     }
     virtual void visit(AstRedOr* nodep, AstNUser*) {

test_regress/t/t_mem_cond.pl

@@ -0,0 +1,18 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+
+compile (
+    );
+
+execute (
+    check_finished=>1,
+    );
+
+ok(1);
+1;

test_regress/t/t_mem_cond.v

@@ -0,0 +1,30 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2006 by Wilson Snyder.
+
+module t (/*AUTOARG*/
+   // Outputs
+   b,
+   // Inputs
+   clk, en, a
+   );
+
+   // bug1017
+
+   input clk;
+
+   input en;
+   input a[1];
+   output logic b[1];
+
+   always_ff @ (posedge clk) begin
+      b <= en ? a : b;
+   end
+
+   always @ (posedge clk) begin
+      $write("*-* All Finished *-*\n");
+      $finish;
+   end
+
+endmodule