forked from github/verilator
Fix type parameter resolution with hash collision.
We incorrectly treated two different struct types the same when passed as an actual parameter to a `parameter type` parameter in an instance, if the actual parameter expression both hash to the same value and the structs have the same struct name. This is now corrected. Fixes #3055.
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@ -31,6 +31,7 @@ Verilator 4.205 devel
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* Allow configure override of AR program (#2999). [ahouska]
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* In XML, show pinIndex information (#2877). [errae233]
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* Fix error on unsupported recursive functions (#2957). [Trefor Southwell]
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* Fix type parameter specialization when struct names are same (#3055). [7FM]
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Verilator 4.204 2021-06-12
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@ -299,9 +299,13 @@ class ParamProcessor final {
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}
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return st;
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}
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string paramValueNumber(AstNode* nodep) {
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static string paramValueKey(const AstNode* nodep) {
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if (const AstRefDType* const refp = VN_CAST_CONST(nodep, RefDType)) {
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nodep = refp->skipRefp();
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}
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string key = nodep->name();
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if (AstIfaceRefDType* ifrtp = VN_CAST(nodep, IfaceRefDType)) {
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if (const AstIfaceRefDType* const ifrtp = VN_CAST_CONST(nodep, IfaceRefDType)) {
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if (ifrtp->cellp() && ifrtp->cellp()->modp()) {
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key = ifrtp->cellp()->modp()->name();
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} else if (ifrtp->ifacep()) {
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@ -309,11 +313,33 @@ class ParamProcessor final {
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} else {
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nodep->v3fatalSrc("Can't parameterize interface without module name");
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}
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} else if (AstBasicDType* bdtp = VN_CAST(nodep, BasicDType)) {
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if (bdtp->isRanged()) {
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key += "[" + cvtToStr(bdtp->left()) + ":" + cvtToStr(bdtp->right()) + "]";
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} else if (const AstNodeUOrStructDType* const dtypep
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= VN_CAST_CONST(nodep, NodeUOrStructDType)) {
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key += " ";
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key += dtypep->verilogKwd();
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key += " {";
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for (const AstNode* memberp = dtypep->membersp(); memberp;
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memberp = memberp->nextp()) {
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key += paramValueKey(memberp);
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key += ";";
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}
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key += "}";
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} else if (const AstMemberDType* const dtypep = VN_CAST_CONST(nodep, MemberDType)) {
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key += " ";
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key += paramValueKey(dtypep->subDTypep());
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} else if (const AstBasicDType* const dtypep = VN_CAST_CONST(nodep, BasicDType)) {
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if (dtypep->isRanged()) {
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key += "[" + cvtToStr(dtypep->left()) + ":" + cvtToStr(dtypep->right()) + "]";
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}
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}
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return key;
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}
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string paramValueNumber(AstNode* nodep) {
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// TODO: This parameter value number lookup via a constructed key string is not
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// particularly robust for type parameters. We should really have a type
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// equivalence predicate function.
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const string key = paramValueKey(nodep);
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V3Hash hash = V3Hasher::uncachedHash(nodep);
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// Force hash collisions -- for testing only
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if (VL_UNLIKELY(v3Global.opt.debugCollision())) hash = V3Hash();
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21
test_regress/t/t_param_type4.pl
Executable file
21
test_regress/t/t_param_type4.pl
Executable file
@ -0,0 +1,21 @@
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#!/usr/bin/env perl
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if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
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# DESCRIPTION: Verilator: Verilog Test driver/expect definition
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#
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# Copyright 2003 by Wilson Snyder. This program is free software; you
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# can redistribute it and/or modify it under the terms of either the GNU
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# Lesser General Public License Version 3 or the Perl Artistic License
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# Version 2.0.
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# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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scenarios(simulator => 1);
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compile(
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);
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execute(
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check_finished => 1,
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);
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ok(1);
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1;
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65
test_regress/t/t_param_type4.v
Normal file
65
test_regress/t/t_param_type4.v
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@ -0,0 +1,65 @@
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2021 by Geza Lore.
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// SPDX-License-Identifier: CC0-1.0
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module t(/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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wire o0, o1;
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sub #(1) a(.i(1'b0), .o(o0));
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sub #(2) b(.i(1'b0), .o(o1));
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always @(posedge clk) begin
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if (o0 != 1'b0) begin
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$write("Bad o0\n");
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$stop;
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end
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if (o1 != 1'b1) begin
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$write("Bad o1\n");
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$stop;
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end
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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module sub
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#(
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parameter int W
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)
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(
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input wire i,
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output wire o
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);
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typedef struct packed {
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logic [W-1:0] a;
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} s;
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sub2 #(s) c(.i(i), .o(o));
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endmodule
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module sub2
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# (
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parameter type T = logic
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)
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(
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input wire i,
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output wire o
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);
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if ($bits(T) % 2 == 1) begin
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assign o = i;
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end else begin
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assign o = ~i;
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end
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endmodule
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24
test_regress/t/t_param_type4_collision.pl
Executable file
24
test_regress/t/t_param_type4_collision.pl
Executable file
@ -0,0 +1,24 @@
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#!/usr/bin/env perl
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if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
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# DESCRIPTION: Verilator: Verilog Test driver/expect definition
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#
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# Copyright 2003 by Wilson Snyder. This program is free software; you
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# can redistribute it and/or modify it under the terms of either the GNU
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# Lesser General Public License Version 3 or the Perl Artistic License
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# Version 2.0.
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# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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scenarios(simulator => 1);
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top_filename("t/t_param_type4.v");
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compile(
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verilator_flags2 => ["--debug-collision"]
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);
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execute(
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check_finished => 1,
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);
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ok(1);
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1;
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