forked from github/verilator
Parser: Move disable fork and wait fork down into elaborate stage
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@ -4337,6 +4337,22 @@ public:
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}
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};
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class AstDisableFork : public AstNodeStmt {
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// A "disable fork" statement
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public:
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AstDisableFork(FileLine* fl)
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: ASTGEN_SUPER(fl) {}
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ASTNODE_NODE_FUNCS(DisableFork)
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};
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class AstWaitFork : public AstNodeStmt {
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// A "wait fork" statement
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public:
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AstWaitFork(FileLine* fl)
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: ASTGEN_SUPER(fl) {}
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ASTNODE_NODE_FUNCS(WaitFork)
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};
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class AstReturn : public AstNodeStmt {
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public:
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explicit AstReturn(FileLine* fl, AstNode* lhsp = NULL)
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@ -568,6 +568,14 @@ private:
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// TBD might support only normal join, if so complain about other join flavors
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}
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}
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virtual void visit(AstDisableFork* nodep) VL_OVERRIDE {
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nodep->v3warn(E_UNSUPPORTED, "Unsupported: disable fork statements");
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VL_DO_DANGLING(nodep->unlinkFrBack()->deleteTree(), nodep);
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}
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virtual void visit(AstWaitFork* nodep) VL_OVERRIDE {
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nodep->v3warn(E_UNSUPPORTED, "Unsupported: wait fork statements");
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VL_DO_DANGLING(nodep->unlinkFrBack()->deleteTree(), nodep);
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}
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virtual void visit(AstToLowerN* nodep) VL_OVERRIDE {
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if (m_vup->prelim()) {
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iterateCheckString(nodep, "LHS", nodep->lhsp(), BOTH);
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@ -3039,7 +3039,7 @@ statement_item<nodep>: // IEEE: statement_item
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//
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// // IEEE: disable_statement
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| yDISABLE idAny/*hierarchical_identifier-task_or_block*/ ';' { $$ = new AstDisable($1,*$2); }
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| yDISABLE yFORK ';' { $$ = NULL; BBUNSUP($1, "Unsupported: disable fork statements"); }
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| yDISABLE yFORK ';' { $$ = new AstDisableFork($1); }
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// // IEEE: event_trigger
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| yP_MINUSGT idDotted/*hierarchical_identifier-event*/ ';'
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{ // AssignDly because we don't have stratified queue, and need to
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@ -3080,7 +3080,7 @@ statement_item<nodep>: // IEEE: statement_item
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//
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// // IEEE: wait_statement
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| yWAIT '(' expr ')' stmtBlock { $$ = NULL; BBUNSUP($1, "Unsupported: wait statements"); }
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| yWAIT yFORK ';' { $$ = NULL; BBUNSUP($1, "Unsupported: wait fork statements"); }
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| yWAIT yFORK ';' { $$ = new AstWaitFork($1); }
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//UNSUP yWAIT_ORDER '(' hierarchical_identifierList ')' action_block { UNSUP }
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//
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// // IEEE: procedural_assertion_statement
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13
test_regress/t/t_fork_disable.out
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13
test_regress/t/t_fork_disable.out
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@ -0,0 +1,13 @@
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%Error-UNSUPPORTED: t/t_fork_disable.v:12:7: Unsupported: fork statements
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: ... In instance t
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12 | fork
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| ^~~~
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%Error-UNSUPPORTED: t/t_fork_disable.v:16:7: Unsupported: disable fork statements
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: ... In instance t
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16 | disable fork;
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| ^~~~~~~
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%Error-UNSUPPORTED: t/t_fork_disable.v:17:7: Unsupported: wait fork statements
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: ... In instance t
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17 | wait fork;
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| ^~~~
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%Error: Exiting due to
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20
test_regress/t/t_fork_disable.pl
Executable file
20
test_regress/t/t_fork_disable.pl
Executable file
@ -0,0 +1,20 @@
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#!/usr/bin/env perl
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if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
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# DESCRIPTION: Verilator: Verilog Test driver/expect definition
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#
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# Copyright 2019 by Wilson Snyder. This program is free software; you
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# can redistribute it and/or modify it under the terms of either the GNU
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# Lesser General Public License Version 3 or the Perl Artistic License
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# Version 2.0.
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# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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scenarios(linter => 1);
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lint(
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verilator_flags2 => ['--lint-only'],
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fails => 1,
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expect_filename => $Self->{golden_filename},
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);
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ok(1);
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1;
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22
test_regress/t/t_fork_disable.v
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22
test_regress/t/t_fork_disable.v
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@ -0,0 +1,22 @@
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2020 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t(/*AUTOARG*/);
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logic never;
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initial begin
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fork
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#10;
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#10;
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join_none
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disable fork;
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wait fork;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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