Improve internal code coverage

nodist/code_coverage.dat

@@ -57,6 +57,7 @@ exclude_line_regexp(qr/(\bv3fatalSrc\b
 # Exclude for branch coverage only
 exclude_branch_regexp(qr/(\bdebug\(\)
                          |\bassert\(
+                         |\bBROKEN_RTK\(
                          |\bSELF_CHECK)/x);
 
 1;

src/V3Number.cpp

@@ -1775,16 +1775,6 @@ V3Number& V3Number::opShiftL(const V3Number& lhs, const V3Number& rhs) {
 //======================================================================
 // Ops - Arithmetic
 
-V3Number& V3Number::opAbsS(const V3Number& lhs) {
-    // op i, L(lhs) bit return
-    NUM_ASSERT_OP_ARGS1(lhs);
-    if (lhs.isFourState()) return setAllBitsX();
-    if (lhs.isNegative()) {
-        return opNegate(lhs);
-    } else {
-        return opAssign(lhs);
-    }
-}
 V3Number& V3Number::opNegate(const V3Number& lhs) {
     // op i, L(lhs) bit return
     NUM_ASSERT_OP_ARGS1(lhs);

src/V3Number.h

@@ -348,7 +348,6 @@ public:
     V3Number& opLogOr(const V3Number& lhs, const V3Number& rhs);
     V3Number& opLogEq(const V3Number& lhs, const V3Number& rhs);
     V3Number& opLogIf(const V3Number& lhs, const V3Number& rhs);
-    V3Number& opAbsS(const V3Number& lhs);
     V3Number& opNegate(const V3Number& lhs);
     V3Number& opAdd(const V3Number& lhs, const V3Number& rhs);
     V3Number& opSub(const V3Number& lhs, const V3Number& rhs);

test_regress/t/t_debug_emitv.out

@@ -175,6 +175,7 @@ module Vt_debug_emitv;
         if ((32'sh5 != t.i)) begin
             $stop;
         end
+        t.sum = $urandom;
     end
     /*verilator public_flat_rw @(posedge clk)@(negedge 
                                                clk) t.pubflat*/

test_regress/t/t_debug_emitv.pl

@@ -13,7 +13,7 @@ scenarios(vlt => 1);
 lint(
     # We also have dump-tree turned on, so hit a lot of AstNode*::dump() functions
     # Likewise XML
-    v_flags => ["--lint-only --dump-treei 9 --debug-emitv"],
+    v_flags => ["--lint-only --dump-treei 9 --dump-treei-V3EmitV 9 --debug-emitv"],
     );
 
 files_identical("$Self->{obj_dir}/$Self->{VM_PREFIX}__preorder.v", $Self->{golden_filename});

test_regress/t/t_debug_emitv.v

@@ -25,9 +25,13 @@ module t (/*AUTOARG*/
    typedef struct {
       logic signed [2:0] a;
    } us_t;
+   typedef union {
+      logic a;
+   } union_t;
 
    const ps_t ps[3];
    us_t us;
+   union_t unu;
 
    int            array[3];
    initial array = '{1,2,3};
@@ -140,6 +144,9 @@ module t (/*AUTOARG*/
       $display("%% [%t] [%t] to=%o td=%d", $time, $realtime, $time, $time);
       $sscanf("foo=5", "foo=%d", i);
       if (i != 5) $stop;
+
+      sum = $random;
+      sum = $urandom;
    end
 endmodule
 
@@ -151,4 +158,30 @@ module sub();
       if (v == 0) return 33;
       return {31'd0, v[2]} + 32'd1;
    endfunction
+   real r;
+   initial begin
+      r = 1.0;
+      r = $log10(r);
+      r = $ln(r);
+      r = $exp(r);
+      r = $sqrt(r);
+      r = $floor(r);
+      r = $ceil(r);
+      r = $sin(r);
+      r = $cos(r);
+      r = $tan(r);
+      r = $asin(r);
+      r = $acos(r);
+      r = $atan(r);
+      r = $sinh(r);
+      r = $cosh(r);
+      r = $tanh(r);
+      r = $asinh(r);
+      r = $acosh(r);
+      r = $atanh(r);
+   end
 endmodule
+
+package p;
+   logic pkgvar;
+endpackage

test_regress/t/t_flag_hier1_bad.out

@@ -0,0 +1,3 @@
+%Error: --hierarchical must not be set with --hierarchical-child or --hierarchical-block
+%Error: --hierarchical-block must be set when --hierarchical-child is set
+%Error: Exiting due to

test_regress/t/t_flag_hier1_bad.pl

@@ -0,0 +1,25 @@
+#!/usr/bin/env perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+scenarios(vlt => 1);
+top_filename("t/t_hier_block.v");
+
+lint(
+    fails => 1,
+    verilator_flags2 => ['--hierarchical',
+                         '--hierarchical-child',
+                         'modName',
+                     ],
+    expect_filename => $Self->{golden_filename},
+    );
+
+ok(1);
+
+1;

test_regress/t/t_flag_mmd.pl

@@ -0,0 +1,20 @@
+#!/usr/bin/env perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+scenarios(vlt => 1);
+
+compile(
+    verilator_flags2 => ["-MMD -MP"],
+    );
+
+file_grep("$Self->{obj_dir}/Vt_flag_mmd__ver.d", qr!t/t_flag_mmd.v!x);
+
+ok(1);
+1;

test_regress/t/t_flag_mmd.v

@@ -0,0 +1,8 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2016 by Wilson Snyder.
+// SPDX-License-Identifier: CC0-1.0
+
+module t;
+endmodule

test_regress/t/t_math_equal.v

@@ -45,13 +45,17 @@ module t (/*AUTOARG*/
 	 //
 	 if (5'd10 != 5'b1010) $stop;
 	 if (5'd10 != 5'd10) $stop;
+	 if (5'd10 != 5'd1_0) $stop;
 	 if (5'd10 != 5'ha) $stop;
 	 if (5'd10 != 5'o12) $stop;
+	 if (5'd10 != 5'o1_2) $stop;
 	 if (5'd10 != 5'B 1010) $stop;
+	 if (5'd10 != 5'B 10_10) $stop;
 	 if (5'd10 != 5'D10) $stop;
 	 if (5'd10 != 5'H a) $stop;
 	 if (5'd10 != 5 'O 12) $stop;
 	 if (24'h29cbb8 != 24'o12345670) $stop;
+	 if (24'h29__cbb8 != 24'o123456__70) $stop;
 	 if (6'b111xxx !== 6'o7x) $stop;
 	 if (6'b111??? !== 6'o7?) $stop;
 	 if (6'b111zzz !== 6'o7z) $stop;

test_regress/t/t_pp_recursedef_bad.out

@@ -0,0 +1,2 @@
+%Error: t/t_pp_recursedef_bad.v:9:8012: Recursive `define substitution: `RECURSE
+%Error: Exiting due to

test_regress/t/t_pp_recursedef_bad.pl

@@ -0,0 +1,19 @@
+#!/usr/bin/env perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+scenarios(vlt => 1);
+
+lint(
+    fails => 1,
+    expect_filename => $Self->{golden_filename},
+    );
+
+ok(1);
+1;

test_regress/t/t_pp_recursedef_bad.v

@@ -0,0 +1,13 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2020 by Wilson Snyder.
+// SPDX-License-Identifier: CC0-1.0
+
+module t;
+`define RECURSE `RECURSE
+   `RECURSE
+
+     initial $stop; // Should have failed
+
+endmodule