From ab502c51962f0a88b70a24aea2467cfd17e0cdfa Mon Sep 17 00:00:00 2001 From: Wilson Snyder Date: Fri, 3 Mar 2023 19:26:15 -0500 Subject: [PATCH] Fix coverage of class methods (#3998). --- Changes | 3 +- include/verilated_types.h | 4 +- src/V3CCtors.cpp | 3 + src/V3Class.cpp | 5 + src/V3Coverage.cpp | 5 +- src/V3EmitCHeaders.cpp | 2 +- src/V3EmitCImp.cpp | 2 +- test_regress/t/t_cover_line.out | 42 ++ test_regress/t/t_cover_line.v | 25 + test_regress/t/t_cover_line_trace.out | 753 +++++++++++++------------- 10 files changed, 463 insertions(+), 381 deletions(-) diff --git a/Changes b/Changes index 0f533c39e..0b9d4febd 100644 --- a/Changes +++ b/Changes @@ -21,6 +21,7 @@ Verilator 5.007 devel * Add lint warning on always_comb multidriven (#3888) (#3939). [Adam Bagley] * Add warning on ++/-- over expressions with potential side effects (#3976). [Krzysztof Boroński] * Add error on mixing .name and by-port instantiations. +* Removed deprecated --cdc option. * Support unpacked unions. * Support interface classes and class implements. * Support global clocking and $global_clock. @@ -32,7 +33,6 @@ Verilator 5.007 devel * Support static function variables (#3830). [Ryszard Rozak, Antmicro Ltd] * Support vpiDefName (#3906) (#3931). [Andrew Nolte] * Support recursive methods (#3987). [Ryszard Rozak, Antmicro Ltd] -* Removed deprecated --cdc option. * Fix real parameters of infinity and NaN. * Fix pattern assignment to unpacked structs (#3510). [Mostafa Garnal] * Fix single-element replication to dynarray/unpacked/queue (#3548). [Gustav Svensk] @@ -62,6 +62,7 @@ Verilator 5.007 devel * Fix timing delays to not truncate below 64 bits (#3973) (#3982). [Felix Neumärker] * Fix cmake on macOS to mark weak symbols with -U linker flag (#3978) (#3979). [Peter Debacker] * Fix UNDRIVEN warning seg fault (#3989). [Felix Neumärker] +* Fix coverage of class methods (#3998). [Tim Paine] * Fix packed array structure replication. * Fix enum.next(0) and enum.prev(0). diff --git a/include/verilated_types.h b/include/verilated_types.h index 8598e8eb5..cb7265e32 100644 --- a/include/verilated_types.h +++ b/include/verilated_types.h @@ -1169,7 +1169,9 @@ public: explicit VlClassRef(VlNull){}; template VlClassRef(VlDeleter& deleter, T_Args&&... args) - : m_objp{new T_Class{std::forward(args)...}} { + // () required here to avoid narrowing conversion warnings, + // when a new() has an e.g. CData type and passed a 1U. + : m_objp{new T_Class(std::forward(args)...)} { m_objp->m_deleterp = &deleter; refCountInc(); } diff --git a/src/V3CCtors.cpp b/src/V3CCtors.cpp index 76453af5f..c70e11b2a 100644 --- a/src/V3CCtors.cpp +++ b/src/V3CCtors.cpp @@ -155,6 +155,9 @@ private: V3CCtorsBuilder configure_coverage{nodep, "_configure_coverage", VCtorType::COVERAGE}; for (AstNode* np = nodep->stmtsp(); np; np = np->nextp()) { if (AstCoverDecl* const coverp = VN_CAST(np, CoverDecl)) { + // ... else we don't have a static VlSym to be able to coverage insert + UASSERT_OBJ(!VN_IS(nodep, Class), coverp, + "CoverDecl should be in class's package, not class itself"); np = coverp->backp(); configure_coverage.add(coverp->unlinkFrBack()); } diff --git a/src/V3Class.cpp b/src/V3Class.cpp index 755c94663..61513782a 100644 --- a/src/V3Class.cpp +++ b/src/V3Class.cpp @@ -156,6 +156,11 @@ private: // m_toScopeMoves.push_back(std::make_pair(nodep, m_classScopep)); //} } + void visit(AstCoverDecl* nodep) override { + // Need to declare coverage in package, where we have access to symbol table + iterateChildren(nodep); + if (m_classPackagep) m_classPackagep->addStmtsp(nodep->unlinkFrBack()); + } void visit(AstInitial* nodep) override { // But not AstInitialAutomatic, which remains under the class iterateChildren(nodep); diff --git a/src/V3Coverage.cpp b/src/V3Coverage.cpp index 88e61becf..340668e71 100644 --- a/src/V3Coverage.cpp +++ b/src/V3Coverage.cpp @@ -124,7 +124,10 @@ private: UINFO(9, "new " << declp << endl); AstCoverInc* const incp = new AstCoverInc{fl, declp}; - if (!trace_var_name.empty() && v3Global.opt.traceCoverage()) { + if (!trace_var_name.empty() + && v3Global.opt.traceCoverage() + // No module handle to trace inside classes + && !VN_IS(m_modp, Class)) { FileLine* const fl_nowarn = new FileLine{incp->fileline()}; fl_nowarn->modifyWarnOff(V3ErrorCode::UNUSEDSIGNAL, true); AstVar* const varp = new AstVar{fl_nowarn, VVarType::MODULETEMP, trace_var_name, diff --git a/src/V3EmitCHeaders.cpp b/src/V3EmitCHeaders.cpp index 3b0ef1abe..eadea126f 100644 --- a/src/V3EmitCHeaders.cpp +++ b/src/V3EmitCHeaders.cpp @@ -161,7 +161,7 @@ class EmitCHeader final : public EmitCConstInit { puts("void " + protect("__Vconfigure") + "(bool first);\n"); } - if (v3Global.opt.coverage()) { + if (v3Global.opt.coverage() && !VN_IS(modp, Class)) { decorateFirst(first, section); puts("void __vlCoverInsert("); puts(v3Global.opt.threads() ? "std::atomic" : "uint32_t"); diff --git a/src/V3EmitCImp.cpp b/src/V3EmitCImp.cpp index efd8d6c22..8bfc9fcfc 100644 --- a/src/V3EmitCImp.cpp +++ b/src/V3EmitCImp.cpp @@ -455,9 +455,9 @@ class EmitCImp final : EmitCFunc { emitCtorImp(modp); emitConfigureImp(modp); emitDestructorImp(modp); + emitCoverageImp(); } emitSavableImp(modp); - emitCoverageImp(); } else { // From `systemc_implementation emitTextSection(modp, VNType::atScImp); diff --git a/test_regress/t/t_cover_line.out b/test_regress/t/t_cover_line.out index ca00845b8..dfb4ee40e 100644 --- a/test_regress/t/t_cover_line.out +++ b/test_regress/t/t_cover_line.out @@ -248,6 +248,39 @@ end endmodule + class Cls; + bit m_toggle; +%000001 function new(bit toggle); +-000001 point: comment=block +%000001 m_toggle = toggle; +-000001 point: comment=block +%000000 if (m_toggle) begin // CHECK_COVER(0,"top.$unit::Cls",1) +-000001 point: comment=if +-000000 point: comment=else +%000001 $write(""); +-000001 point: comment=if + end + endfunction + 000011 static function void fstatic(bit toggle); ++000011 point: comment=block +%000000 if (1) begin // CHECK_COVER(0,"top.$unit::Cls",1) ++000011 point: comment=if +-000000 point: comment=else + 000011 $write(""); ++000011 point: comment=if + end + endfunction + 000011 function void fauto(); ++000011 point: comment=block +%000000 if (m_toggle) begin // CHECK_COVER(0,"top.$unit::Cls",1) ++000011 point: comment=if +-000000 point: comment=else + 000011 $write(""); ++000011 point: comment=if + end + endfunction + endclass + module tsk (/*AUTOARG*/ // Inputs clk, toggle @@ -281,6 +314,15 @@ -000001 point: comment=if end end + 000011 begin ++000011 point: comment=block +%000001 Cls c = new(1'b1); +-000001 point: comment=block + 000011 c.fauto(); ++000011 point: comment=block + 000011 Cls::fstatic(1'b1); ++000011 point: comment=block + end endtask endmodule diff --git a/test_regress/t/t_cover_line.v b/test_regress/t/t_cover_line.v index 6b03de5e7..49da71cdc 100644 --- a/test_regress/t/t_cover_line.v +++ b/test_regress/t/t_cover_line.v @@ -175,6 +175,26 @@ module beta (/*AUTOARG*/ end endmodule +class Cls; + bit m_toggle; + function new(bit toggle); + m_toggle = toggle; + if (m_toggle) begin // CHECK_COVER(0,"top.$unit::Cls",1) + $write(""); + end + endfunction + static function void fstatic(bit toggle); + if (1) begin // CHECK_COVER(0,"top.$unit::Cls",1) + $write(""); + end + endfunction + function void fauto(); + if (m_toggle) begin // CHECK_COVER(0,"top.$unit::Cls",1) + $write(""); + end + endfunction +endclass + module tsk (/*AUTOARG*/ // Inputs clk, toggle @@ -198,6 +218,11 @@ module tsk (/*AUTOARG*/ $write("[%0t] Got external pulse\n", $time); end end + begin + Cls c = new(1'b1); + c.fauto(); + Cls::fstatic(1'b1); + end endtask endmodule diff --git a/test_regress/t/t_cover_line_trace.out b/test_regress/t/t_cover_line_trace.out index 9c6365e91..e32c0cd15 100644 --- a/test_regress/t/t_cover_line_trace.out +++ b/test_regress/t/t_cover_line_trace.out @@ -1,98 +1,98 @@ $version Generated by VerilatedVcd $end -$date Sat Dec 18 13:32:31 2021 $end $timescale 1ps $end $scope module top $end - $var wire 1 W clk $end + $var wire 1 X clk $end $scope module t $end - $var wire 1 W clk $end - $var wire 32 & cyc [31:0] $end - $var wire 8 ' cyc_copy [7:0] $end - $var wire 1 % toggle $end - $var wire 32 ; vlCoverageLineTrace_t_cover_line__102_elsif [31:0] $end - $var wire 32 < vlCoverageLineTrace_t_cover_line__105_elsif [31:0] $end - $var wire 32 = vlCoverageLineTrace_t_cover_line__112_else [31:0] $end - $var wire 32 > vlCoverageLineTrace_t_cover_line__112_if [31:0] $end - $var wire 32 X vlCoverageLineTrace_t_cover_line__119_block [31:0] $end + $var wire 1 X clk $end + $var wire 32 ' cyc [31:0] $end + $var wire 8 ( cyc_copy [7:0] $end + $var wire 1 & toggle $end + $var wire 32 < vlCoverageLineTrace_t_cover_line__102_elsif [31:0] $end + $var wire 32 = vlCoverageLineTrace_t_cover_line__105_elsif [31:0] $end + $var wire 32 > vlCoverageLineTrace_t_cover_line__112_else [31:0] $end + $var wire 32 ? vlCoverageLineTrace_t_cover_line__112_if [31:0] $end + $var wire 32 Y vlCoverageLineTrace_t_cover_line__119_block [31:0] $end $var wire 32 # vlCoverageLineTrace_t_cover_line__15_block [31:0] $end $var wire 32 $ vlCoverageLineTrace_t_cover_line__18_block [31:0] $end - $var wire 32 ( vlCoverageLineTrace_t_cover_line__47_block [31:0] $end - $var wire 32 ) vlCoverageLineTrace_t_cover_line__48_else [31:0] $end - $var wire 32 * vlCoverageLineTrace_t_cover_line__48_if [31:0] $end - $var wire 32 + vlCoverageLineTrace_t_cover_line__52_else [31:0] $end - $var wire 32 , vlCoverageLineTrace_t_cover_line__52_if [31:0] $end - $var wire 32 - vlCoverageLineTrace_t_cover_line__53_else [31:0] $end - $var wire 32 . vlCoverageLineTrace_t_cover_line__53_if [31:0] $end - $var wire 32 / vlCoverageLineTrace_t_cover_line__58_else [31:0] $end - $var wire 32 0 vlCoverageLineTrace_t_cover_line__58_if [31:0] $end - $var wire 32 1 vlCoverageLineTrace_t_cover_line__59_else [31:0] $end - $var wire 32 2 vlCoverageLineTrace_t_cover_line__59_if [31:0] $end - $var wire 32 3 vlCoverageLineTrace_t_cover_line__65_else [31:0] $end - $var wire 32 4 vlCoverageLineTrace_t_cover_line__65_if [31:0] $end - $var wire 32 5 vlCoverageLineTrace_t_cover_line__66_else [31:0] $end - $var wire 32 6 vlCoverageLineTrace_t_cover_line__66_if [31:0] $end - $var wire 32 7 vlCoverageLineTrace_t_cover_line__75_elsif [31:0] $end - $var wire 32 8 vlCoverageLineTrace_t_cover_line__79_elsif [31:0] $end - $var wire 32 9 vlCoverageLineTrace_t_cover_line__83_else [31:0] $end - $var wire 32 : vlCoverageLineTrace_t_cover_line__83_if [31:0] $end - $var wire 32 ] vlCoverageLineTrace_t_cover_line__92_block [31:0] $end - $var wire 32 ^ vlCoverageLineTrace_t_cover_line__93_block [31:0] $end - $var wire 32 _ vlCoverageLineTrace_t_cover_line__96_block [31:0] $end - $var wire 32 ` vlCoverageLineTrace_t_cover_line__97_block [31:0] $end + $var wire 32 ) vlCoverageLineTrace_t_cover_line__47_block [31:0] $end + $var wire 32 * vlCoverageLineTrace_t_cover_line__48_else [31:0] $end + $var wire 32 + vlCoverageLineTrace_t_cover_line__48_if [31:0] $end + $var wire 32 , vlCoverageLineTrace_t_cover_line__52_else [31:0] $end + $var wire 32 - vlCoverageLineTrace_t_cover_line__52_if [31:0] $end + $var wire 32 . vlCoverageLineTrace_t_cover_line__53_else [31:0] $end + $var wire 32 / vlCoverageLineTrace_t_cover_line__53_if [31:0] $end + $var wire 32 0 vlCoverageLineTrace_t_cover_line__58_else [31:0] $end + $var wire 32 1 vlCoverageLineTrace_t_cover_line__58_if [31:0] $end + $var wire 32 2 vlCoverageLineTrace_t_cover_line__59_else [31:0] $end + $var wire 32 3 vlCoverageLineTrace_t_cover_line__59_if [31:0] $end + $var wire 32 4 vlCoverageLineTrace_t_cover_line__65_else [31:0] $end + $var wire 32 5 vlCoverageLineTrace_t_cover_line__65_if [31:0] $end + $var wire 32 6 vlCoverageLineTrace_t_cover_line__66_else [31:0] $end + $var wire 32 7 vlCoverageLineTrace_t_cover_line__66_if [31:0] $end + $var wire 32 8 vlCoverageLineTrace_t_cover_line__75_elsif [31:0] $end + $var wire 32 9 vlCoverageLineTrace_t_cover_line__79_elsif [31:0] $end + $var wire 32 : vlCoverageLineTrace_t_cover_line__83_else [31:0] $end + $var wire 32 ; vlCoverageLineTrace_t_cover_line__83_if [31:0] $end + $var wire 32 ^ vlCoverageLineTrace_t_cover_line__92_block [31:0] $end + $var wire 32 _ vlCoverageLineTrace_t_cover_line__93_block [31:0] $end + $var wire 32 ` vlCoverageLineTrace_t_cover_line__96_block [31:0] $end + $var wire 32 a vlCoverageLineTrace_t_cover_line__97_block [31:0] $end $scope module a1 $end - $var wire 1 W clk $end - $var wire 1 % toggle $end - $var wire 32 ? vlCoverageLineTrace_t_cover_line__132_block [31:0] $end - $var wire 32 @ vlCoverageLineTrace_t_cover_line__133_else [31:0] $end - $var wire 32 A vlCoverageLineTrace_t_cover_line__133_if [31:0] $end - $var wire 32 B vlCoverageLineTrace_t_cover_line__137_else [31:0] $end + $var wire 1 X clk $end + $var wire 1 & toggle $end + $var wire 32 @ vlCoverageLineTrace_t_cover_line__132_block [31:0] $end + $var wire 32 A vlCoverageLineTrace_t_cover_line__133_else [31:0] $end + $var wire 32 B vlCoverageLineTrace_t_cover_line__133_if [31:0] $end + $var wire 32 C vlCoverageLineTrace_t_cover_line__137_else [31:0] $end $upscope $end $scope module a2 $end - $var wire 1 W clk $end - $var wire 1 % toggle $end - $var wire 32 C vlCoverageLineTrace_t_cover_line__132_block [31:0] $end - $var wire 32 D vlCoverageLineTrace_t_cover_line__133_else [31:0] $end - $var wire 32 E vlCoverageLineTrace_t_cover_line__133_if [31:0] $end - $var wire 32 F vlCoverageLineTrace_t_cover_line__137_else [31:0] $end + $var wire 1 X clk $end + $var wire 1 & toggle $end + $var wire 32 D vlCoverageLineTrace_t_cover_line__132_block [31:0] $end + $var wire 32 E vlCoverageLineTrace_t_cover_line__133_else [31:0] $end + $var wire 32 F vlCoverageLineTrace_t_cover_line__133_if [31:0] $end + $var wire 32 G vlCoverageLineTrace_t_cover_line__137_else [31:0] $end $upscope $end $scope module b1 $end - $var wire 1 W clk $end - $var wire 1 % toggle $end - $var wire 32 K vlCoverageLineTrace_t_cover_line__156_block [31:0] $end - $var wire 32 L vlCoverageLineTrace_t_cover_line__158_else [31:0] $end - $var wire 32 b vlCoverageLineTrace_t_cover_line__158_if [31:0] $end - $var wire 32 M vlCoverageLineTrace_t_cover_line__162_else [31:0] $end - $var wire 32 N vlCoverageLineTrace_t_cover_line__162_if [31:0] $end - $var wire 32 O vlCoverageLineTrace_t_cover_line__166_else [31:0] $end + $var wire 1 X clk $end + $var wire 1 & toggle $end + $var wire 32 L vlCoverageLineTrace_t_cover_line__156_block [31:0] $end + $var wire 32 M vlCoverageLineTrace_t_cover_line__158_else [31:0] $end + $var wire 32 c vlCoverageLineTrace_t_cover_line__158_if [31:0] $end + $var wire 32 N vlCoverageLineTrace_t_cover_line__162_else [31:0] $end + $var wire 32 O vlCoverageLineTrace_t_cover_line__162_if [31:0] $end + $var wire 32 P vlCoverageLineTrace_t_cover_line__166_else [31:0] $end $upscope $end $scope module b2 $end - $var wire 1 W clk $end - $var wire 1 % toggle $end - $var wire 32 P vlCoverageLineTrace_t_cover_line__156_block [31:0] $end - $var wire 32 Q vlCoverageLineTrace_t_cover_line__158_else [31:0] $end - $var wire 32 c vlCoverageLineTrace_t_cover_line__158_if [31:0] $end - $var wire 32 R vlCoverageLineTrace_t_cover_line__162_else [31:0] $end - $var wire 32 S vlCoverageLineTrace_t_cover_line__162_if [31:0] $end - $var wire 32 T vlCoverageLineTrace_t_cover_line__166_else [31:0] $end + $var wire 1 X clk $end + $var wire 1 & toggle $end + $var wire 32 Q vlCoverageLineTrace_t_cover_line__156_block [31:0] $end + $var wire 32 R vlCoverageLineTrace_t_cover_line__158_else [31:0] $end + $var wire 32 d vlCoverageLineTrace_t_cover_line__158_if [31:0] $end + $var wire 32 S vlCoverageLineTrace_t_cover_line__162_else [31:0] $end + $var wire 32 T vlCoverageLineTrace_t_cover_line__162_if [31:0] $end + $var wire 32 U vlCoverageLineTrace_t_cover_line__166_else [31:0] $end $upscope $end $scope module o1 $end - $var wire 1 W clk $end - $var wire 1 % toggle $end - $var wire 32 G vlCoverageLineTrace_t_cover_line__220_block [31:0] $end - $var wire 32 H vlCoverageLineTrace_t_cover_line__221_else [31:0] $end - $var wire 32 I vlCoverageLineTrace_t_cover_line__221_if [31:0] $end - $var wire 32 J vlCoverageLineTrace_t_cover_line__224_else [31:0] $end - $var wire 32 a vlCoverageLineTrace_t_cover_line__224_if [31:0] $end + $var wire 1 X clk $end + $var wire 1 & toggle $end + $var wire 32 H vlCoverageLineTrace_t_cover_line__245_block [31:0] $end + $var wire 32 I vlCoverageLineTrace_t_cover_line__246_else [31:0] $end + $var wire 32 J vlCoverageLineTrace_t_cover_line__246_if [31:0] $end + $var wire 32 K vlCoverageLineTrace_t_cover_line__249_else [31:0] $end + $var wire 32 b vlCoverageLineTrace_t_cover_line__249_if [31:0] $end $upscope $end $scope module t1 $end - $var wire 1 W clk $end - $var wire 1 % toggle $end - $var wire 32 U vlCoverageLineTrace_t_cover_line__187_block [31:0] $end - $var wire 32 Y vlCoverageLineTrace_t_cover_line__191_block [31:0] $end - $var wire 32 Z vlCoverageLineTrace_t_cover_line__194_else [31:0] $end - $var wire 32 [ vlCoverageLineTrace_t_cover_line__194_if [31:0] $end - $var wire 32 V vlCoverageLineTrace_t_cover_line__197_else [31:0] $end - $var wire 32 \ vlCoverageLineTrace_t_cover_line__197_if [31:0] $end + $var wire 1 X clk $end + $var wire 1 & toggle $end + $var wire 32 V vlCoverageLineTrace_t_cover_line__207_block [31:0] $end + $var wire 32 Z vlCoverageLineTrace_t_cover_line__211_block [31:0] $end + $var wire 32 [ vlCoverageLineTrace_t_cover_line__214_else [31:0] $end + $var wire 32 \ vlCoverageLineTrace_t_cover_line__214_if [31:0] $end + $var wire 32 W vlCoverageLineTrace_t_cover_line__217_else [31:0] $end + $var wire 32 ] vlCoverageLineTrace_t_cover_line__217_if [31:0] $end + $var wire 32 % vlCoverageLineTrace_t_cover_line__222_block [31:0] $end $upscope $end $upscope $end $upscope $end @@ -102,10 +102,10 @@ $enddefinitions $end #0 b00000000000000000000000000000001 # b00000000000000000000000000000001 $ -0% -b00000000000000000000000000000001 & -b00000001 ' -b00000000000000000000000000000000 ( +b00000000000000000000000000000001 % +0& +b00000000000000000000000000000001 ' +b00000001 ( b00000000000000000000000000000000 ) b00000000000000000000000000000000 * b00000000000000000000000000000000 + @@ -152,8 +152,8 @@ b00000000000000000000000000000000 S b00000000000000000000000000000000 T b00000000000000000000000000000000 U b00000000000000000000000000000000 V -0W -b00000000000000000000000000000000 X +b00000000000000000000000000000000 W +0X b00000000000000000000000000000000 Y b00000000000000000000000000000000 Z b00000000000000000000000000000000 [ @@ -165,362 +165,363 @@ b00000000000000000000000000000000 ` b00000000000000000000000000000000 a b00000000000000000000000000000000 b b00000000000000000000000000000000 c +b00000000000000000000000000000000 d #10 -b00000000000000000000000000000010 & -b00000010 ' -b00000000000000000000000000000001 ( -b00000000000000000000000000000001 * +b00000000000000000000000000000010 ' +b00000010 ( +b00000000000000000000000000000001 ) b00000000000000000000000000000001 + -b00000000000000000000000000000001 - -b00000000000000000000000000000001 / -b00000000000000000000000000000001 1 -b00000000000000000000000000000001 3 -b00000000000000000000000000000001 5 -b00000000000000000000000000000001 9 -b00000000000000000000000000000001 = -b00000000000000000000000000000001 ? -b00000000000000000000000000000001 @ -b00000000000000000000000000000001 B -b00000000000000000000000000000001 C -b00000000000000000000000000000001 D -b00000000000000000000000000000001 F -b00000000000000000000000000000001 G -b00000000000000000000000000000001 H -b00000000000000000000000000000001 K -b00000000000000000000000000000001 L -b00000000000000000000000000000001 M -b00000000000000000000000000000001 O -b00000000000000000000000000000001 P -b00000000000000000000000000000001 Q -b00000000000000000000000000000001 R -b00000000000000000000000000000001 T -b00000000000000000000000000000001 U -b00000000000000000000000000000001 V -1W -b00000000000000000000000000000001 Y -b00000000000000000000000000000001 Z -#15 -0W -#20 -b00000000000000000000000000000011 & -b00000011 ' -b00000000000000000000000000000010 ( -b00000000000000000000000000000010 * -b00000000000000000000000000000010 + -b00000000000000000000000000000010 - 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