forked from github/verilator
Support assignment expressions.
This commit is contained in:
Wilson Snyder
parent
21d80cdfa1
commit
aacb38b776
1
Changes
1
Changes
@ -18,6 +18,7 @@ Verilator 5.003 devel
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* Support randcase.
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* Support pre_randomize and post_randomize.
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* Support $timeunit and $timeprecision.
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* Support assignment expressions.
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* Add ENUMVALUE warning when value misused for enum (#726).
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* Internal AST improvements, also affect XML format (#3721). [Geza Lore]
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* Change ENDLABEL from warning into an error.
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@ -237,6 +237,7 @@ private:
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// METHODS
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void iterateNewStmt(AstNode* nodep) {
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if (m_scopep) {
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VL_RESTORER(m_logicVertexp);
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UINFO(4, " STMT " << nodep << endl);
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m_logicVertexp = new CdcLogicVertex(&m_graph, m_scopep, nodep, m_domainp);
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if (m_domainp && m_domainp->hasClocked()) { // To/from a flop
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@ -247,7 +248,6 @@ private:
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m_logicVertexp->dstDomainSet(true);
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}
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iterateChildren(nodep);
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m_logicVertexp = nullptr;
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if (false && debug() >= 9) {
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UINFO(9, "Trace Logic:\n");
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@ -680,6 +680,7 @@ private:
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}
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}
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void visit(AstAssignDly* nodep) override {
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VL_RESTORER(m_inDly);
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m_inDly = true;
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iterateChildren(nodep);
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m_inDly = false;
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@ -505,6 +505,8 @@ private:
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nodep->deleteTree();
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}
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void visit(AstAssignDly* nodep) override {
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VL_RESTORER(m_inDly);
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VL_RESTORER(m_nextDlyp);
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m_inDly = true;
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m_nextDlyp
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= VN_CAST(nodep->nextp(), AssignDly); // Next assignment in same block, maybe nullptr.
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@ -537,8 +539,6 @@ private:
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} else {
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iterateChildren(nodep);
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}
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m_inDly = false;
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m_nextDlyp = nullptr;
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}
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void visit(AstVarRef* nodep) override {
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@ -190,18 +190,18 @@ class DataflowExtractVisitor final : public VNVisitor {
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}
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void visit(AstAssignForce* nodep) override {
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VL_RESTORER(m_inForceReleaseLhs);
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iterate(nodep->rhsp());
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UASSERT_OBJ(!m_inForceReleaseLhs, nodep, "Should not nest");
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m_inForceReleaseLhs = true;
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iterate(nodep->lhsp());
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m_inForceReleaseLhs = false;
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}
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void visit(AstRelease* nodep) override {
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VL_RESTORER(m_inForceReleaseLhs);
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UASSERT_OBJ(!m_inForceReleaseLhs, nodep, "Should not nest");
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m_inForceReleaseLhs = true;
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iterate(nodep->lhsp());
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m_inForceReleaseLhs = false;
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}
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void visit(AstNodeExpr* nodep) override { iterateChildrenConst(nodep); }
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@ -828,12 +828,13 @@ private:
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void visit(AstNodeStmt* nodep) override {
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if (nodep->user1SetOnce()) return; // Process once
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VL_RESTORER(m_stmtp);
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m_stmtp = nodep;
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iterateChildren(nodep);
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m_stmtp = nullptr;
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}
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void visit(AstNodeAssign* nodep) override {
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if (nodep->user1SetOnce()) return; // Process once
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VL_RESTORER(m_stmtp);
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m_stmtp = nodep;
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iterateChildren(nodep);
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bool did = false;
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@ -869,7 +870,6 @@ private:
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}
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// Cleanup common code
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if (did) VL_DO_DANGLING(nodep->unlinkFrBack()->deleteTree(), nodep);
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m_stmtp = nullptr;
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}
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//--------------------
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@ -396,15 +396,15 @@ class OrderBuildVisitor final : public VNVisitor {
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void visit(AstAssignW* nodep) override { iterateLogic(nodep); }
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void visit(AstAssignPre* nodep) override {
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UASSERT_OBJ(!m_inPre, nodep, "Should not nest");
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VL_RESTORER(m_inPre);
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m_inPre = true;
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iterateLogic(nodep);
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m_inPre = false;
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}
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void visit(AstAssignPost* nodep) override {
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UASSERT_OBJ(!m_inPost, nodep, "Should not nest");
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VL_RESTORER(m_inPost);
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m_inPost = true;
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iterateLogic(nodep);
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m_inPost = false;
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}
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//--- Verilator concoctions
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@ -759,6 +759,9 @@ private:
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if (jumpingOver(nodep)) return;
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if (!optimizable()) return; // Accelerate
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checkNodeInfo(nodep);
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VL_RESTORER(m_inDlyAssign);
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if (VN_IS(nodep, AssignForce)) {
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clearOptimizable(nodep, "Force");
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} else if (VN_IS(nodep, AssignDly)) {
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@ -793,7 +796,6 @@ private:
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assignOutValue(nodep, vscp, fetchValue(nodep->rhsp()));
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}
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}
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m_inDlyAssign = false;
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}
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void visit(AstArraySel* nodep) override {
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checkNodeInfo(nodep);
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@ -156,9 +156,9 @@ class SliceVisitor final : public VNVisitor {
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// This will potentially call this function again to resolve next level of slicing
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return;
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}
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VL_RESTORER(m_assignp);
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m_assignp = nodep;
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iterateChildren(nodep);
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m_assignp = nullptr;
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}
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}
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@ -340,10 +340,10 @@ protected:
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// of what is before vs. after
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void visit(AstAssignDly* nodep) override {
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VL_RESTORER(m_inDly);
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m_inDly = true;
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UINFO(4, " ASSIGNDLY " << nodep << endl);
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iterateChildren(nodep);
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m_inDly = false;
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}
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void visit(AstVarRef* nodep) override {
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if (!m_stmtStackps.empty()) {
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@ -252,6 +252,7 @@ private:
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// VISITORS
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void visit(AstNodeAssign* nodep) override {
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VL_RESTORER(m_ops);
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m_ops = 0;
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m_assignStep++;
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iterateAndNextNull(nodep->rhsp());
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@ -360,7 +361,7 @@ private:
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doDeletes();
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}
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void visit(AstNode* nodep) override {
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m_ops++;
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++m_ops;
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if (!nodep->isSubstOptimizable()) m_ops = SUBST_MAX_OPS_NA;
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iterateChildren(nodep);
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}
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@ -189,9 +189,9 @@ private:
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iterateChildren(nodep);
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}
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void visit(AstAssignW* nodep) override {
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VL_RESTORER(m_assignwp);
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m_assignwp = nodep;
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VL_DO_DANGLING(iterateChildren(nodep), nodep); // May delete nodep.
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m_assignwp = nullptr;
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}
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void visit(AstNodeFTaskRef* nodep) override {
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// Includes handling AstMethodCall, AstNew
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@ -1229,6 +1229,8 @@ class TristateVisitor final : public TristateBaseVisitor {
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void visit(AstOr* nodep) override { visitAndOr(nodep, false); }
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void visitAssign(AstNodeAssign* nodep) {
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VL_RESTORER(m_alhs);
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VL_RESTORER(m_currentStrength);
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if (m_graphing) {
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if (AstAssignW* assignWp = VN_CAST(nodep, AssignW)) addToAssignmentList(assignWp);
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@ -1279,9 +1281,6 @@ class TristateVisitor final : public TristateBaseVisitor {
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}
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}
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iterateAndNextNull(nodep->lhsp());
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// back to default strength
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m_currentStrength = VStrength::STRONG;
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m_alhs = false;
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}
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}
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void visit(AstAssignW* nodep) override { visitAssign(nodep); }
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117
src/verilog.y
117
src/verilog.y
@ -2691,18 +2691,30 @@ genvar_initialization<nodep>: // ==IEEE: genvar_initialization
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;
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genvar_iteration<nodep>: // ==IEEE: genvar_iteration
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varRefBase '=' expr { $$ = new AstAssign($2,$1,$3); }
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| varRefBase yP_PLUSEQ expr { $$ = new AstAssign($2,$1,new AstAdd ($2,$1->cloneTree(true),$3)); }
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| varRefBase yP_MINUSEQ expr { $$ = new AstAssign($2,$1,new AstSub ($2,$1->cloneTree(true),$3)); }
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| varRefBase yP_TIMESEQ expr { $$ = new AstAssign($2,$1,new AstMul ($2,$1->cloneTree(true),$3)); }
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| varRefBase yP_DIVEQ expr { $$ = new AstAssign($2,$1,new AstDiv ($2,$1->cloneTree(true),$3)); }
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| varRefBase yP_MODEQ expr { $$ = new AstAssign($2,$1,new AstModDiv ($2,$1->cloneTree(true),$3)); }
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| varRefBase yP_ANDEQ expr { $$ = new AstAssign($2,$1,new AstAnd ($2,$1->cloneTree(true),$3)); }
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| varRefBase yP_OREQ expr { $$ = new AstAssign($2,$1,new AstOr ($2,$1->cloneTree(true),$3)); }
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| varRefBase yP_XOREQ expr { $$ = new AstAssign($2,$1,new AstXor ($2,$1->cloneTree(true),$3)); }
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| varRefBase yP_SLEFTEQ expr { $$ = new AstAssign($2,$1,new AstShiftL ($2,$1->cloneTree(true),$3)); }
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| varRefBase yP_SRIGHTEQ expr { $$ = new AstAssign($2,$1,new AstShiftR ($2,$1->cloneTree(true),$3)); }
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| varRefBase yP_SSRIGHTEQ expr { $$ = new AstAssign($2,$1,new AstShiftRS($2,$1->cloneTree(true),$3)); }
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varRefBase '=' expr
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{ $$ = new AstAssign{$2, $1, $3}; }
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| varRefBase yP_PLUSEQ expr
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{ $$ = new AstAssign{$2, $1, new AstAdd{$2, $1->cloneTree(true), $3}}; }
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| varRefBase yP_MINUSEQ expr
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{ $$ = new AstAssign{$2, $1, new AstSub{$2, $1->cloneTree(true), $3}}; }
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| varRefBase yP_TIMESEQ expr
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{ $$ = new AstAssign{$2, $1, new AstMul{$2, $1->cloneTree(true), $3}}; }
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| varRefBase yP_DIVEQ expr
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{ $$ = new AstAssign{$2, $1, new AstDiv{$2, $1->cloneTree(true), $3}}; }
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| varRefBase yP_MODEQ expr
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{ $$ = new AstAssign{$2, $1, new AstModDiv{$2, $1->cloneTree(true), $3}}; }
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| varRefBase yP_ANDEQ expr
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{ $$ = new AstAssign{$2, $1, new AstAnd{$2, $1->cloneTree(true), $3}}; }
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| varRefBase yP_OREQ expr
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{ $$ = new AstAssign{$2, $1, new AstOr{$2, $1->cloneTree(true), $3}}; }
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| varRefBase yP_XOREQ expr
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{ $$ = new AstAssign{$2, $1, new AstXor{$2, $1->cloneTree(true), $3}}; }
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| varRefBase yP_SLEFTEQ expr
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{ $$ = new AstAssign{$2, $1, new AstShiftL{$2, $1->cloneTree(true), $3}}; }
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| varRefBase yP_SRIGHTEQ expr
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{ $$ = new AstAssign{$2, $1, new AstShiftR{$2, $1->cloneTree(true), $3}}; }
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| varRefBase yP_SSRIGHTEQ expr
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{ $$ = new AstAssign{$2, $1, new AstShiftRS{$2, $1->cloneTree(true), $3}}; }
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// // inc_or_dec_operator
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// When support ++ as a real AST type, maybe AstWhile::precondsp() becomes generic AstNodeExprStmt?
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| yP_PLUSPLUS varRefBase
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@ -3425,17 +3437,28 @@ foperator_assignment<nodep>: // IEEE: operator_assignment (for first part of
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| fexprLvalue '=' yD_FOPEN '(' expr ',' expr ')' { $$ = new AstFOpen($3,$1,$5,$7); }
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//
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//UNSUP ~f~exprLvalue yP_PLUS(etc) expr { UNSUP }
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| fexprLvalue yP_PLUSEQ expr { $$ = new AstAssign($2,$1,new AstAdd ($2,$1->cloneTree(true),$3)); }
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| fexprLvalue yP_MINUSEQ expr { $$ = new AstAssign($2,$1,new AstSub ($2,$1->cloneTree(true),$3)); }
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| fexprLvalue yP_TIMESEQ expr { $$ = new AstAssign($2,$1,new AstMul ($2,$1->cloneTree(true),$3)); }
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| fexprLvalue yP_DIVEQ expr { $$ = new AstAssign($2,$1,new AstDiv ($2,$1->cloneTree(true),$3)); }
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| fexprLvalue yP_MODEQ expr { $$ = new AstAssign($2,$1,new AstModDiv ($2,$1->cloneTree(true),$3)); }
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| fexprLvalue yP_ANDEQ expr { $$ = new AstAssign($2,$1,new AstAnd ($2,$1->cloneTree(true),$3)); }
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| fexprLvalue yP_OREQ expr { $$ = new AstAssign($2,$1,new AstOr ($2,$1->cloneTree(true),$3)); }
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| fexprLvalue yP_XOREQ expr { $$ = new AstAssign($2,$1,new AstXor ($2,$1->cloneTree(true),$3)); }
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| fexprLvalue yP_SLEFTEQ expr { $$ = new AstAssign($2,$1,new AstShiftL ($2,$1->cloneTree(true),$3)); }
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| fexprLvalue yP_SRIGHTEQ expr { $$ = new AstAssign($2,$1,new AstShiftR ($2,$1->cloneTree(true),$3)); }
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| fexprLvalue yP_SSRIGHTEQ expr { $$ = new AstAssign($2,$1,new AstShiftRS($2,$1->cloneTree(true),$3)); }
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| fexprLvalue yP_PLUSEQ expr
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{ $$ = new AstAssign{$2, $1, new AstAdd{$2, $1->cloneTree(true), $3}}; }
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| fexprLvalue yP_MINUSEQ expr
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{ $$ = new AstAssign{$2, $1, new AstSub{$2, $1->cloneTree(true), $3}}; }
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| fexprLvalue yP_TIMESEQ expr
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{ $$ = new AstAssign{$2, $1, new AstMul{$2, $1->cloneTree(true), $3}}; }
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| fexprLvalue yP_DIVEQ expr
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{ $$ = new AstAssign{$2, $1, new AstDiv{$2, $1->cloneTree(true), $3}}; }
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| fexprLvalue yP_MODEQ expr
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{ $$ = new AstAssign{$2, $1, new AstModDiv{$2, $1->cloneTree(true), $3}}; }
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| fexprLvalue yP_ANDEQ expr
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{ $$ = new AstAssign{$2, $1, new AstAnd{$2, $1->cloneTree(true), $3}}; }
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| fexprLvalue yP_OREQ expr
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{ $$ = new AstAssign{$2, $1, new AstOr{$2, $1->cloneTree(true), $3}}; }
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| fexprLvalue yP_XOREQ expr
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{ $$ = new AstAssign{$2, $1, new AstXor{$2, $1->cloneTree(true), $3}}; }
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| fexprLvalue yP_SLEFTEQ expr
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{ $$ = new AstAssign{$2, $1, new AstShiftL{$2, $1->cloneTree(true), $3}}; }
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| fexprLvalue yP_SRIGHTEQ expr
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{ $$ = new AstAssign{$2, $1, new AstShiftR{$2, $1->cloneTree(true), $3}}; }
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| fexprLvalue yP_SSRIGHTEQ expr
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{ $$ = new AstAssign{$2, $1, new AstShiftRS{$2, $1->cloneTree(true), $3}}; }
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//UNSUP replace above with:
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//UNSUP BISONPRE_COPY(operator_assignment,{s/~f~/f/g}) // {copied}
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;
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@ -4403,18 +4426,42 @@ expr<nodeExprp>: // IEEE: part of expression/constant_expression/
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//
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// // IEEE: '(' operator_assignment ')'
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// // Need exprScope of variable_lvalue to prevent conflict
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//UNSUP '(' ~p~exprScope '=' expr ')' { UNSUP }
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//UNSUP '(' ~p~exprScope yP_PLUSEQ expr ')' { UNSUP }
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//UNSUP '(' ~p~exprScope yP_MINUSEQ expr ')' { UNSUP }
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//UNSUP '(' ~p~exprScope yP_TIMESEQ expr ')' { UNSUP }
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//UNSUP '(' ~p~exprScope yP_DIVEQ expr ')' { UNSUP }
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//UNSUP '(' ~p~exprScope yP_MODEQ expr ')' { UNSUP }
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//UNSUP '(' ~p~exprScope yP_ANDEQ expr ')' { UNSUP }
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//UNSUP '(' ~p~exprScope yP_OREQ expr ')' { UNSUP }
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//UNSUP '(' ~p~exprScope yP_XOREQ expr ')' { UNSUP }
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//UNSUP '(' ~p~exprScope yP_SLEFTEQ expr ')' { UNSUP }
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//UNSUP '(' ~p~exprScope yP_SRIGHTEQ expr ')' { UNSUP }
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//UNSUP '(' ~p~exprScope yP_SSRIGHTEQ expr ')' { UNSUP }
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| '(' ~p~exprScope '=' expr ')'
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{ $$ = new AstExprStmt{$1, new AstAssign{$3, $2, $4},
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$2->cloneTree(true)}; }
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| '(' ~p~exprScope yP_PLUSEQ expr ')'
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{ $$ = new AstExprStmt{$1, new AstAssign{$3, $2, new AstAdd{$3, $2->cloneTree(true), $4}},
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$2->cloneTree(true)}; }
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| '(' ~p~exprScope yP_MINUSEQ expr ')'
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{ $$ = new AstExprStmt{$1, new AstAssign{$3, $2, new AstSub{$3, $2->cloneTree(true), $4}},
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$2->cloneTree(true)}; }
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| '(' ~p~exprScope yP_TIMESEQ expr ')'
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{ $$ = new AstExprStmt{$1, new AstAssign{$3, $2, new AstMul{$3, $2->cloneTree(true), $4}},
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$2->cloneTree(true)}; }
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| '(' ~p~exprScope yP_DIVEQ expr ')'
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{ $$ = new AstExprStmt{$1, new AstAssign{$3, $2, new AstDiv{$3, $2->cloneTree(true), $4}},
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$2->cloneTree(true)}; }
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| '(' ~p~exprScope yP_MODEQ expr ')'
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{ $$ = new AstExprStmt{$1, new AstAssign{$3, $2, new AstModDiv{$3, $2->cloneTree(true), $4}},
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$2->cloneTree(true)}; }
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| '(' ~p~exprScope yP_ANDEQ expr ')'
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{ $$ = new AstExprStmt{$1, new AstAssign{$3, $2, new AstAnd{$3, $2->cloneTree(true), $4}},
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$2->cloneTree(true)}; }
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| '(' ~p~exprScope yP_OREQ expr ')'
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{ $$ = new AstExprStmt{$1, new AstAssign{$3, $2, new AstOr{$3, $2->cloneTree(true), $4}},
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$2->cloneTree(true)}; }
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| '(' ~p~exprScope yP_XOREQ expr ')'
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{ $$ = new AstExprStmt{$1, new AstAssign{$3, $2, new AstXor{$3, $2->cloneTree(true), $4}},
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$2->cloneTree(true)}; }
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| '(' ~p~exprScope yP_SLEFTEQ expr ')'
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{ $$ = new AstExprStmt{$1, new AstAssign{$3, $2, new AstShiftL{$3, $2->cloneTree(true), $4}},
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$2->cloneTree(true)}; }
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| '(' ~p~exprScope yP_SRIGHTEQ expr ')'
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{ $$ = new AstExprStmt{$1, new AstAssign{$3, $2, new AstShiftR{$3, $2->cloneTree(true), $4}},
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$2->cloneTree(true)}; }
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| '(' ~p~exprScope yP_SSRIGHTEQ expr ')'
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{ $$ = new AstExprStmt{$1, new AstAssign{$3, $2, new AstShiftRS{$3, $2->cloneTree(true), $4}},
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$2->cloneTree(true)}; }
|
||||
//
|
||||
// // IEEE: expression binary_operator expression
|
||||
| ~l~expr '+' ~r~expr { $$ = new AstAdd ($2,$1,$3); }
|
||||
|
||||
21
test_regress/t/t_assign_expr.pl
Executable file
21
test_regress/t/t_assign_expr.pl
Executable file
@ -0,0 +1,21 @@
|
||||
#!/usr/bin/env perl
|
||||
if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
|
||||
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
|
||||
#
|
||||
# Copyright 2022 by Wilson Snyder. This program is free software; you
|
||||
# can redistribute it and/or modify it under the terms of either the GNU
|
||||
# Lesser General Public License Version 3 or the Perl Artistic License
|
||||
# Version 2.0.
|
||||
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
|
||||
|
||||
scenarios(simulator => 1);
|
||||
|
||||
compile(
|
||||
);
|
||||
|
||||
execute(
|
||||
check_finished => 1,
|
||||
);
|
||||
|
||||
ok(1);
|
||||
1;
|
||||
77
test_regress/t/t_assign_expr.v
Normal file
77
test_regress/t/t_assign_expr.v
Normal file
@ -0,0 +1,77 @@
|
||||
// DESCRIPTION: Verilator: Verilog Test module
|
||||
//
|
||||
// This file ONLY is placed under the Creative Commons Public Domain, for
|
||||
// any use, without warranty, 2022 by Wilson Snyder.
|
||||
// SPDX-License-Identifier: CC0-1.0
|
||||
|
||||
`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0);
|
||||
|
||||
module t(/*AUTOARG*/);
|
||||
|
||||
int a;
|
||||
int b;
|
||||
int i;
|
||||
|
||||
initial begin
|
||||
a = 10;
|
||||
i = (a = 2);
|
||||
`checkd(a, 2); `checkd(i, 2);
|
||||
|
||||
a = 10;
|
||||
i = (a += 2);
|
||||
`checkd(a, 12); `checkd(i, 12);
|
||||
|
||||
a = 10;
|
||||
i = (a -= 2);
|
||||
`checkd(a, 8); `checkd(i, 8);
|
||||
|
||||
a = 10;
|
||||
i = (a *= 2);
|
||||
`checkd(a, 20); `checkd(i, 20);
|
||||
|
||||
a = 10;
|
||||
i = (a /= 2);
|
||||
`checkd(a, 5); `checkd(i, 5);
|
||||
|
||||
a = 11;
|
||||
i = (a %= 2);
|
||||
`checkd(a, 1); `checkd(i, 1);
|
||||
|
||||
a = 10;
|
||||
i = (a &= 2);
|
||||
`checkd(a, 2); `checkd(i, 2);
|
||||
|
||||
a = 8;
|
||||
i = (a |= 2);
|
||||
`checkd(a, 10); `checkd(i, 10);
|
||||
|
||||
a = 10;
|
||||
i = (a ^= 2);
|
||||
`checkd(a, 8); `checkd(i, 8);
|
||||
|
||||
a = 10;
|
||||
i = (a <<= 2);
|
||||
`checkd(a, 40); `checkd(i, 40);
|
||||
|
||||
a = 10;
|
||||
i = (a >>= 2);
|
||||
`checkd(a, 2); `checkd(i, 2);
|
||||
|
||||
a = 10;
|
||||
i = (a >>>= 2);
|
||||
`checkd(a, 2); `checkd(i, 2);
|
||||
|
||||
a = 10;
|
||||
i = (a = (b = 5));
|
||||
`checkd(a, 5); `checkd(i, 5); `checkd(b, 5);
|
||||
|
||||
a = 10;
|
||||
b = 6;
|
||||
i = ((a += (b += 1) + 1));
|
||||
`checkd(a, 18); `checkd(i, 18); `checkd(b, 7);
|
||||
|
||||
$write("*-* All Finished *-*\n");
|
||||
$finish;
|
||||
end
|
||||
|
||||
endmodule
|
||||
Loading…
Reference in New Issue
Block a user