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Tests: Remove unintended t_0 test

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This commit is contained in:
Wilson Snyder 2023-03-16 18:44:28 -04:00
parent 66e4656a8e
commit a9b07fe7d7
2 changed files with 0 additions and 42 deletions
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21
test_regress/t/t_0.pl
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@ -1,21 +0,0 @@
#!/usr/bin/env perl
if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2003 by Wilson Snyder. This program is free software; you
# can redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
scenarios(simulator => 1);
compile(
);
execute(
check_finished => 1,
);
ok(1);
1;

21
test_regress/t/t_0.v
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@ -1,21 +0,0 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2009 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/);
enum int unsigned {
FIVE_INT = 5
} FI;
int array5i[FIVE_INT];
initial begin
if ($size(array5i) != 5) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
endmodule