Fix double conversion on half of conditional.

src/V3Width.cpp

@@ -426,13 +426,12 @@ private:
         nodep->dtypeSetUInt64();  // A pointer, but not that it matters
     }
 
-    // Special cases.  So many....
     virtual void visit(AstNodeCond* nodep) VL_OVERRIDE {
-        // op=cond?expr1:expr2
-        // Signed: Output signed iff RHS & THS signed  (presumed, not in IEEE)
+        // op = cond ? expr1 : expr2
         // See IEEE-2012 11.4.11 and Table 11-21.
         //   LHS is self-determined
-        //   Width: max(RHS,THS)
+        //   Width: max(RHS, THS)
+        //   Signed: Output signed iff RHS & THS signed  (presumed, not in IEEE)
         //   Real: Output real if either expression is real, non-real argument gets converted
         if (m_vup->prelim()) {  // First stage evaluation
             // Just once, do the conditional, expect one bit out.
@@ -4550,14 +4549,17 @@ private:
         } else if (expDTypep->isDouble() && underp->isDouble()) {  // Also good
             underp = userIterateSubtreeReturnEdits(underp, WidthVP(SELF, FINAL).p());
         } else if (expDTypep->isDouble() && !underp->isDouble()) {
+            AstNode* oldp = underp;  // Need FINAL on children; otherwise splice would block it
             underp = spliceCvtD(underp);
-            underp = userIterateSubtreeReturnEdits(underp, WidthVP(SELF, FINAL).p());
+            underp = userIterateSubtreeReturnEdits(oldp, WidthVP(SELF, FINAL).p());
         } else if (!expDTypep->isDouble() && underp->isDouble()) {
+            AstNode* oldp = underp;  // Need FINAL on children; otherwise splice would block it
             underp = spliceCvtS(underp, true, expDTypep->width());  // Round RHS
-            underp = userIterateSubtreeReturnEdits(underp, WidthVP(SELF, FINAL).p());
+            underp = userIterateSubtreeReturnEdits(oldp, WidthVP(SELF, FINAL).p());
         } else if (expDTypep->isString() && !underp->dtypep()->isString()) {
+            AstNode* oldp = underp;  // Need FINAL on children; otherwise splice would block it
             underp = spliceCvtString(underp);
-            underp = userIterateSubtreeReturnEdits(underp, WidthVP(SELF, FINAL).p());
+            underp = userIterateSubtreeReturnEdits(oldp, WidthVP(SELF, FINAL).p());
         } else {
             AstBasicDType* expBasicp = expDTypep->basicp();
             AstBasicDType* underBasicp = underp->dtypep()->basicp();

test_regress/t/t_math_yosys.pl

@@ -0,0 +1,21 @@
+#!/usr/bin/env perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2019 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+scenarios(simulator => 1);
+
+compile(
+    );
+
+execute(
+    check_finished => 1,
+    );
+
+ok(1);
+1;

test_regress/t/t_math_yosys.v

@@ -0,0 +1,84 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2020 Claire Wolf.
+// SPDX-License-Identifier: CC0-1.0
+
+module t(/*AUTOARG*/
+   // Inputs
+   clk
+   );
+   input clk;
+
+   integer cyc=0;
+
+   /*AUTOWIRE*/
+   // Beginning of automatic wires (for undeclared instantiated-module outputs)
+   wire [7:0]           y1;                     // From d1 of demo_001.v
+   wire [7:0]           y2;                     // From d1 of demo_001.v
+   wire [7:0]           y3;                     // From d1 of demo_001.v
+   wire [7:0]           y4;                     // From d1 of demo_001.v
+   wire [31:0]          z0;                     // From d2 of demo_002.v
+   wire [31:0]          z1;                     // From d2 of demo_002.v
+   wire [31:0]          z2;                     // From d2 of demo_002.v
+   wire [31:0]          z3;                     // From d2 of demo_002.v
+   // End of automatics
+
+   demo_001 d1(/*AUTOINST*/
+               // Outputs
+               .y1                      (y1[7:0]),
+               .y2                      (y2[7:0]),
+               .y3                      (y3[7:0]),
+               .y4                      (y4[7:0]));
+   demo_002 d2(/*AUTOINST*/
+               // Outputs
+               .z0                      (z0[31:0]),
+               .z1                      (z1[31:0]),
+               .z2                      (z2[31:0]),
+               .z3                      (z3[31:0]));
+
+   // Test loop
+   always @ (posedge clk) begin
+      cyc <= cyc + 1;
+      if (y1 !== 8'h7b) $stop;
+      if (y2 !== 8'h7c) $stop;
+      if (y3 !== 8'h7b) $stop;
+      if (y4 !== 8'h7c) $stop;
+      if (z0 !== 32'h00000000) $stop;
+      if (z1 !== 32'hffffffff) $stop;
+      if (z2 !== 32'hffffffff) $stop;
+      if (z3 !== 32'hffffffff) $stop;
+      if (cyc == 99) begin
+         $write("*-* All Finished *-*\n");
+         $finish;
+      end
+   end
+endmodule
+
+module demo_001(y1, y2, y3, y4);
+   output [7:0] y1, y2, y3, y4;
+
+   // verilator lint_off REALCVT
+   localparam [7:0] p1 = 123.45;
+   localparam real p2 = 123.45;
+   localparam real p3 = 123;
+   localparam p4 = 123.45;
+
+   // verilator lint_off WIDTH
+   assign y1 = p1 + 0.2;
+   assign y2 = p2 + 0.2;
+   assign y3 = p3 + 0.2;
+   assign y4 = p4 + 0.2;
+   // verilator lint_on WIDTH
+endmodule
+
+module demo_002(z0, z1, z2, z3);
+   output [31:0] z0, z1, z2, z3;
+
+   // verilator lint_off WIDTH
+   assign z0 = 1'bx >= (-1 * -1.17);
+   // verilator lint_on WIDTH
+   assign z1 = 1 ?  1 ?  -1 : 'd0 : 0.0;
+   assign z2 = 1 ? -1 :   1 ? 'd0 : 0.0;
+   assign z3 = 1 ? -1 : 'd0;
+endmodule